Compiler Mapping Communication in Parallel Processing Networks
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Solution Overview
Problem
The high cost and performance limitations of Field Programmable Gate Arrays (FPGAs) compared to Application Specific Integrated Circuits (ASICs) in parallel processing environments, along with the need for efficient communication mapping in tiled integrated circuits.
Innovation Solution
A method for generating instructions in integrated circuits with multiple processor cores interconnected by an interconnection network, involving mapping communication operations to resources, determining correspondence among communication operations, and generating switch instructions for efficient communication routing, allowing for automatic generation of static network instructions and reducing programming complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used for reconfigurability, then adaptability is improved, but performance and power efficiency deteriorate
Solution Approach 1:
The system is divided into multiple independent tiles, each containing processor cores and communication resources. This segmentation allows parallel execution across tiles while maintaining reconfigurability at the tile level, thus improving performance without sacrificing adaptability.
Solution Approach 2:
A compiler acts as an intermediary between high-level C code and the underlying hardware architecture. The compiler automatically generates switch instructions and maps communication operations to the interconnection network, enabling programmers to write simple code while achieving optimized performance through automated resource allocation and communication mapping.
2Productivity
If manual communication mapping is implemented, then communication efficiency is improved, but programming complexity increases
Solution Approach 1:
The compiler automatically performs communication mapping and generates switch instructions without requiring manual intervention from programmers. The system serves itself by translating high-level communication operations into optimized low-level instructions, maintaining communication efficiency while eliminating programming complexity.
Solution Approach 2:
The compiler serves as an intermediary that automatically maps communication operations to the interconnection network. It analyzes C code, determines correspondence among communication operations, and generates appropriate switch instructions, thus achieving efficient communication mapping without increasing programming complexity.
3Ease of operation
If automatic compiler generation is used, then ease of programming is improved, but communication optimization may deteriorate
Solution Approach 1:
The compiler acts as an intelligent intermediary that automatically analyzes C code, determines correspondence among communication operations, and generates optimized switch instructions. This automation maintains ease of programming while achieving communication optimization through systematic resource allocation and routing.
Solution Approach 2:
The compiler dynamically adjusts communication parameters such as routing paths, switch configurations, and resource allocation based on the analyzed C code. By automatically optimizing these parameters, the system achieves communication optimization while maintaining ease of programming through high-level language abstraction.
Data Source
AI summary
An the integrated circuit comprises a plurality of processor cores interconnected by an interconnection network. A method for generating instructions to be executed in the integrated circuit comprises accepting a plurality of programs, at least some of the programs including one or more communication operations to communicate with other programs; mapping each program to one or more of the processor cores; determining correspondence among communication operations in the programs; and mapping communication for corresponding communication operations to resources associated with the interconnection network.