Compiler Memory Barrier Insertion for Weak Memory Ordering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multithreaded programs running on a weak memory model experience weak memory ordering issues due to differing instruction semantics across memory models, leading to logic errors and inaccurate output results.
Innovation Solution
A method and apparatus that automatically rectify weak memory ordering by classifying instructions in a read/write instruction set, inserting memory barrier instructions before target instructions, and utilizing optimization policies to minimize unnecessary barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory barrier instructions are inserted to fix weak memory ordering problems, then program execution order is corrected, but program execution efficiency deteriorates
Solution Approach 1:
The patent applies local quality by selectively inserting memory barrier instructions only at specific target instruction locations where weak memory ordering problems occur, rather than uniformly across all instructions. The compilation device classifies instructions to identify target instructions that require memory barriers, thereby applying the barrier mechanism locally only where needed to maintain correctness while minimizing performance impact.
2Productivity
If automatic repair methods are used to fix weak memory ordering problems, then repair efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the compilation device to automatically classify instructions, identify target instructions requiring memory barriers, and insert appropriate barriers without manual intervention. The system performs self-diagnosis and self-repair of weak memory ordering problems through automated analysis and transformation of the instruction sequence during compilation.
3Reliability
If memory barrier instructions are inserted before all read/write instructions, then memory ordering is ensured, but unnecessary barriers increase execution overhead
Solution Approach 1:
The patent applies partial action by inserting memory barrier instructions only for the subset of read/write instructions that are classified as target instructions requiring ordering guarantees, rather than applying barriers to all read/write instructions uniformly. This selective approach ensures sufficient memory ordering protection while avoiding the excessive overhead of unnecessary barriers.
Data Source
Figure 1~2
Figure 3
Figure 4a(a)~4a(c)
AI summary
This application relates to the field of computer technologies, and discloses a method and an apparatus for rectifying a weak memory ordering problem. The method can automatically rectify a weak memory ordering problem in a multithreaded program in a compiling phase of the multithreaded program. The method includes: determining a read/write instruction set in to-be-repaired code; classifying instructions in the read/write instruction set to determine a target instruction; and inserting a memory barrier instruction between a previous read/write instruction of the target instruction and the target instruction, where the read/write instruction set includes a read instruction and/or a write instruction in the to-be-repaired code, and an instruction in the read/write instruction set is used for memory access.