Compiler Modulo Addressing Vectorization for Loop Performance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Processor cores face performance bottlenecks due to the time-consuming nature of executing memory access instructions within loops that utilize modulo operations, as these require repeated execution and are influenced by hardware characteristics.

Innovation Solution

A method and system for modulo addressing vectorization, where a compiler identifies memory access instructions within loops and replaces them with vector invariant or vector modulo addressing access codes, eliminating the need for modulo calculations within the loop by determining if the addresses accessed are periodic induction variables and aligning with vectorization factors, thereby optimizing memory access operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory access instructions are executed within loops using modulo operations, then the processor can handle periodic memory access patterns, but the processing time increases due to repeated execution and hardware characteristics

Engineering Contradiction:

Improvehandling periodic memory access patternsVSAvoidprocessing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The compiler performs preliminary analysis of memory access patterns before loop execution, identifying periodic access patterns and pre-computing vectorized access codes. This preliminary transformation eliminates the need for modulo operations during actual loop execution, reducing processing time while maintaining adaptability to periodic patterns.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical execution of modulo operations within loops with a compiler-generated vectorized access mechanism. The compiler substitutes the runtime modulo calculation with optimized vector invariant or vector modulo addressing access codes that directly compute periodic memory addresses without repeated modulo operations, thereby reducing processing time.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If modulo operations are performed within loops for memory addressing, then the processor can access periodic memory locations, but the hardware characteristics cause the operations to be time-consuming

Engineering Contradiction:

Improvememory access capabilityVSAvoidprocessor efficiency

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The compiler performs preliminary transformation of loop code, identifying modulo operations and replacing them with vectorized access patterns. This preliminary action maintains the ease of accessing periodic memory locations while eliminating the time-consuming modulo operations during execution, thereby improving processor efficiency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the addressing parameters from scalar modulo operations to vectorized addressing modes. By transforming the access pattern parameters to support vector invariant or vector modulo addressing, the system maintains memory access capability while improving productivity through parallel processing and eliminated modulo operations.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If loop instructions are executed multiple times for modulo addressing, then the processor can complete memory access sequences, but the execution time increases

Engineering Contradiction:

Improvememory access sequence completionVSAvoidexecution time

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The compiler merges multiple loop iterations with modulo operations into a single vectorized memory access operation. By combining the functionality of multiple sequential operations into one vectorized instruction, the system maintains reliable memory access sequence completion while significantly reducing the duration of execution.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent substitutes the mechanical execution of multiple loop instructions with a vectorized access mechanism. This substitution maintains the reliability of completing memory access sequences while reducing execution time through parallel processing and elimination of repeated modulo operations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10180829B2System and method for modulo addressing vectorization with invariant code motion

Publication Date: 2019.01.15 NXP USA INC

AI summary

A processing device includes a target processor instruction memory to store a plurality of memory access instructions, and a compiler. A vector invariant candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector invariant access code, and in response: the complier to generate first replacement code that vectorizes the memory access instruction using vector invariant access code, and to replace the memory access instruction with the first replacement code. A vector modulo addressing candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector modulo addressing access code, and in response: the complier to generate second replacement code that vectorizes the memory access instruction using vector modulo addressing code, and to replace the memory access instruction with the second replacement code.