Compiler for Multi-Processor Executables with Dynamic Co-Processor Reconfiguration
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Solution Overview
Problem
Current multi-processor systems face limitations in efficiently processing instructions across heterogeneous processors with different instruction sets, as they lack a mechanism to dynamically reconfigure instruction sets and maintain cache coherency between host processors and co-processors, leading to suboptimal performance and increased programmer workload.
Innovation Solution
A software compiler is developed to generate a single executable that includes instructions for both host processors with fixed instruction sets and dynamically reconfigurable co-processors, allowing the co-processor's instruction set to be dynamically reconfigured to optimize performance, and maintaining cache coherency between host processors and co-processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple homogeneous processors with fixed instruction sets are used, then cache coherency can be maintained, but processing efficiency for different instruction types is limited
Solution Approach 1:
The patent implements dynamically reconfigurable instruction sets in co-processors, allowing the instruction set architecture to change at runtime based on computational needs. This enables the system to adapt between different instruction sets (e.g., x86, ARM, RISC-V) without physical hardware changes, resolving the contradiction between fixed architecture stability and flexible adaptability
2Productivity
If heterogeneous processors with different instruction sets are used, then processing performance is optimized, but cache coherency maintenance becomes difficult
Solution Approach 1:
The patent introduces a cache coherency protocol as an intermediary mechanism that mediates between heterogeneous processors with different instruction sets. This protocol translates and coordinates cache operations across different architectures, maintaining coherency without requiring processors to share the same instruction set, thus resolving the contradiction between performance optimization and reliability
3Adaptability or versatility
If dynamically reconfigurable co-processors are implemented, then instruction set adaptability is improved, but system complexity increases
Solution Approach 1:
The patent segments the processing system into host processors with fixed instruction sets and co-processors with dynamically reconfigurable instruction sets. This segmentation isolates the complexity of reconfiguration to specific components while maintaining simplicity in the host processors, resolving the contradiction between adaptability and overall system complexity
4Ease of operation
If a single executable is generated for multiple instruction sets, then programmer workload is reduced, but compiler complexity increases
Solution Approach 1:
The patent employs a multi-processor compiler as an intermediary that automatically handles the complexity of generating multi-instruction-set executables. The compiler analyzes source code, identifies suitable instruction sets for different computational tasks, and generates appropriate machine code for host processors and co-processors, shielding programmers from compiler complexity while enabling ease of operation
Data Source
AI summary
A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.