Compiler-Defined Opcode Assignment for FPGA Processor Customization
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Solution Overview
Problem
Existing processor architectures are inflexible in reducing the width of the operational code, even when not all functions in the Instruction Set Architecture (ISA) are utilized by end-user software, leading to inefficient resource usage and increased operational code size.
Innovation Solution
A method where a compiler selects and assigns unique operational codes to lists of control signals based on the specific requirements of end-user software, allowing for customization of the processor design, synthesis, and implementation in an integrated circuit, such as an FPGA, to optimize the operational code width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the operational code width is fixed by the ISA to support all possible functions, then the processor can execute any function in the instruction set, but the operational code width cannot be reduced even when not all functions are used, leading to inefficient resource usage
Solution Approach 1:
The patent applies dynamics by making the operational code width adaptable rather than fixed. The compiler analyzes the end-user software to determine which functions are actually used, then dynamically assigns only the necessary operational codes, allowing the effective operational code width to vary based on software requirements while maintaining compatibility with the fixed ISA
Solution Approach 2:
The patent changes the parameter of operational code width based on software analysis. By examining which mnemonics are used in the end-user software and assigning operational codes only to those functions, the system effectively reduces the operational code width parameter while still supporting all required functions, resolving the contradiction between full functional support and code efficiency
2Adaptability or versatility
If all possible functions are included in the ISA, then the processor supports diverse applications, but the operational code width increases, consuming more resources
Solution Approach 1:
The patent extracts only the necessary functions from the full ISA based on software analysis. The compiler identifies which mnemonics are actually used in the end-user software and assigns operational codes only to those extracted functions, eliminating unnecessary operational code assignments and reducing the effective operational code size while maintaining support for diverse required applications
Solution Approach 2:
The patent applies partial action by assigning operational codes selectively rather than universally. Instead of assigning operational codes to all possible ISA functions, the system performs partial assignment based on actual software needs, reducing the quantity of operational codes used while still providing full support for the diverse applications required by the end-user software
Data Source
AI summary
End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.