Compiler Parallelism Scheduling Without Register Spills
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Solution Overview
Problem
Existing compiler techniques for VLIW processors often exceed available processing resources, leading to inefficient execution and register spills, as they prioritize scheduling operations as soon as possible without adequately considering resource constraints.
Innovation Solution
A method that forms data flow graphs, clusters vertices with strong dependencies, schedules them for non-overlapping execution, and iteratively reschedules candidate clusters to optimize execution time while monitoring resource usage, ensuring that processing resources are not exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If vertices are scheduled as soon as possible to maximize parallelism, then execution speed is improved, but processing resources such as registers are exceeded causing inefficient spills to memory
Solution Approach 1:
The compiler dynamically adjusts the scheduling strategy by iteratively rescheduling vertices based on resource availability. Instead of using a static 'as soon as possible' approach, the system continuously evaluates resource constraints and modifies the schedule to balance parallelism with resource limitations, preventing register spills while maintaining execution speed.
Solution Approach 2:
The compiler implements feedback mechanisms by monitoring resource usage during scheduling and using this information to guide subsequent scheduling decisions. The system evaluates whether scheduling a vertex would exceed resource constraints and adjusts the schedule accordingly, creating a closed-loop control system that prevents resource overflow while maximizing parallelism.
2Productivity
If vertices are scheduled to commute with others to improve parallelism, then productivity is improved, but device complexity increases due to arbitrary selection between multiple candidate vertices
Solution Approach 1:
The compiler segments the scheduling problem by dividing vertices into different categories based on their scheduling characteristics. Vertices are grouped according to their readiness conditions and resource requirements, allowing the scheduler to handle different segments with appropriate strategies rather than treating all vertices uniformly, thus reducing scheduling complexity while maintaining parallelism.
Solution Approach 2:
The compiler changes scheduling parameters by adjusting the criteria for vertex selection based on current resource availability and schedule state. Instead of using arbitrary or fixed selection rules, the system dynamically modifies selection parameters to favor vertices that can be scheduled without exceeding resources, thereby reducing complexity while preserving productivity.
Data Source
AI summary
A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added must be made. This data flow graph with these small clusters is then scheduled such that the clusters do not overlap with other clusters or with vertices outside of clusters. This starting point scheduled data flow graph is then subject to iterative processing whereby a window of timestamps is analysed to see if a candidate cluster formed by the parallel execution of the vertices within that window will result in faster execution whilst avoiding exceeding architectural constraints, such as register occupancy. If the rescheduled vertices do improve performance without exceeding architectural constraints, then this new schedule is adopted and the following vertices are subject to an adjustment in their timestamps to account for this. A window at a different point within the schedule is then adopted and an attempted rescheduling examined. This process is repeated until no progress is being made in reducing the overall execution time.