Compiler Partitioning Unit for Cache Block Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing programming technologies require manual partitioning of programs into cache blocks, which is labor-intensive and inefficient, especially for large and complex programs, and can lead to increased overhead due to frequent function calls and returns across small cache blocks.

Innovation Solution

A compiler with a partitioning unit that identifies and extracts subgraphs with a single entry and exit instruction sequence as cache blocks, generating object code for each block and inserting call instructions to manage function calls and returns efficiently, thereby reducing the programmer's workload and optimizing cache usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a program is manually partitioned into cache blocks, then cache access speed is improved, but programmer workload and complexity increase

Engineering Contradiction:
Improvecache access speedVSAvoidprogrammer workload
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The compiler automatically performs program partitioning into cache blocks without requiring programmer intervention. The system analyzes the program structure, identifies suitable partition points, and generates the partitioned code autonomously, allowing the compilation system to serve itself rather than requiring external programmer effort for this task

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The partitioning is performed during the compilation phase before the program is executed. By analyzing control flow graphs and identifying subgraphs with single entry and exit points in advance, the system prepares the optimal cache block structure beforehand, eliminating the need for runtime partitioning decisions and reducing programmer burden

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a program is partitioned into small cache blocks, then cache hit rate is improved, but overhead from function calls and returns increases

Engineering Contradiction:
Improvecache hit rateVSAvoidoverhead from function calls
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the size and structure of cache blocks by analyzing program characteristics. Instead of using fixed small blocks, the compiler identifies subgraphs that can be extracted as cache blocks with optimal sizes, changing the partitioning parameters based on program structure to minimize function call overhead while maintaining cache effectiveness

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The program is segmented into subgraphs based on control flow analysis. Each subgraph represents a logical unit with single entry and exit points, allowing the program to be divided into meaningful cache blocks that reduce unnecessary function calls while maintaining appropriate block sizes for cache efficiency

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If automatic partitioning is implemented, then programmer workload is reduced, but compilation complexity increases

Engineering Contradiction:
Improveprogrammer workloadVSAvoidcompilation complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The compiler acts as an intermediary between the programmer and the cache optimization process. Rather than requiring the programmer to directly manage cache partitioning, the compiler automatically analyzes the program structure, identifies subgraphs, and generates partitioned code, shielding the programmer from complexity while achieving optimization goals

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8645910B2Compiler capable of partitioning program and program partitioning method
Publication Date: 2014.02.04 SONY INTERACTIVE ENTERTAINMENT LLC
  • US8645910B2 patent drawing
  • US8645910B2 patent drawing
  • US8645910B2 patent drawing

AI summary

A program stored in a memory is read, and in a path representing the order of processing instruction sequences forming the program, a subgraph including a sequence of instructions that includes only one instruction at the entry and only one instruction at the exit is identified. At least a part of a source instruction sequence included in the subgraph is extracted as a new program block and stored in a memory. An instruction for calling the instruction sequence in the new program block is inserted in a program block including the source instruction sequence. The program block including the source instruction sequence is then stored in the memory.