Compiler Pattern Reconstruction for SIMT Parallelism Efficiency
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Solution Overview
Problem
Existing parallel computing systems face challenges in applying parallelism to all operations and data structures due to the loss of structural information during the transformation of high-level AI program representations into source code, leading to inefficient code generation and sub-optimal performance.
Innovation Solution
A compile-time approach is employed to reconstruct structural information from SIMT and SIMD programs by identifying parallelism unstructured behavior values (PUBVs) and populating pattern data structures, which are then used by a code generator to produce more efficient executable code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-level representations of AI programs are transformed into source code for SIMT or SIMD software, then the code can be executed on parallel computing systems, but structural information is lost leading to reduced parallelism efficiency
Solution Approach 1:
The patent performs preliminary analysis during compilation to identify operations that contribute to parallelism unstructured behavior values before code generation. By detecting PUBV contribution operations in advance and populating pattern data structures with this information, the system prepares optimization data beforehand, allowing the code generator to produce more efficient parallel code without losing structural information in the transformation process
Solution Approach 2:
The patent introduces pattern data structures as an intermediary between the source code analysis and code generation processes. These data structures capture structural information about parallelism behavior patterns and serve as a bridge, transmitting this information to the code generator to guide the production of optimized parallel code while preventing information loss during the transformation from high-level representation to executable code
2Productivity
If parallelism operations are applied to all operations and data structures, then computational results can be obtained more quickly, but it becomes difficult to apply parallelism to all operations and data structures
Solution Approach 1:
The patent applies local quality by analyzing each operation individually to determine its parallelism characteristics. Instead of uniformly applying parallelism to all operations, the system identifies specific operations that contribute to parallelism unstructured behavior and applies targeted optimizations only where needed, making the parallelism application both effective and adaptable to different operation types
Solution Approach 2:
The patent changes parameters by detecting and analyzing parallelism unstructured behavior values and their contribution operations. By monitoring these parameters during compilation and using them to guide code generation, the system dynamically adjusts the parallelism optimization strategy to match the specific characteristics of each operation and data structure, enabling versatile application across different computational patterns
Data Source
AI summary
A tool analyzes source code of a program that targets a parallel processing system, and searches for parallelism unstructured behavior values that potentially inhibit parallelism efficiency. Example parallelism unstructured behavior values include particular memory addresses, memory masks, control divergences, and instruction predicates, which are identified according to their context and use in the program. The tool also locates program operations that contribute to these values, and determines a source of parallelism structure information in the program. In some scenarios, the tool populates a pattern data structure which is suitable to help guide code generation. Patterns detected include addressing patterns, mask patterns, and thread control patterns. Programs analyzed include single instruction multiple data programs and single instruction multiple thread programs. Code generation guided by the pattern data structure to optimize parallelism efficiency produces smaller and faster program code which consumes less on-chip memory.