Compiler Pipeline Optimization for Embedded Image Processing Memory
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Solution Overview
Problem
Conventional image processing in embedded devices requires significant memory for frame memory allocation, which reduces productivity due to the need for manual calculation and recalculation of processing delay and line memory size, especially in complex processes, and can lead to errors if not accurately calculated.
Innovation Solution
A compiling device that calculates processing delay amounts and line memory sizes automatically, converting process tasks to be executable in a pipeline, thereby reducing memory requirements and improving productivity by generating instruction codes that optimize data access between process tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If frame memory is allocated to hold entire input image data for each process task, then data can be readily accessed by process tasks, but memory area requirement increases significantly (e.g., 40 Mbytes for 20 Mbytes input data)
Solution Approach 1:
The patent extracts only the necessary portion of image data (a few lines around the current processing line) from the entire frame memory, rather than loading the complete frame. This allows process tasks to access required data while significantly reducing the memory area needed for frame memory allocation.
Solution Approach 2:
The patent segments the frame memory into smaller units by processing image data line by line and maintaining only a buffer of recent lines (e.g., 4 lines) in memory. This segmentation approach reduces the overall memory requirement from storing the entire frame to storing only the necessary segment for current processing operations.
2Quantity of substance
If process tasks are modified to execute in a pipeline with processing delay, then memory area requirement is minimized, but calculation complexity and error risk increase due to manual recalculation of processing delay and line memory size
Solution Approach 1:
The patent implements self-service by having the compiler automatically calculate processing delay amounts and line memory sizes based on the source program's access patterns. The compiler analyzes read/write operations, determines necessary delays, and generates optimized pipeline execution codes without requiring manual intervention or recalculation by the user.
Solution Approach 2:
The patent performs preliminary action by having the compiler pre-calculate processing delay amounts and line memory sizes during the compilation phase. This preliminary calculation eliminates the need for manual recalculation during implementation, reducing complexity and error risk while maintaining optimized memory usage.
3Productivity
If manual calculation of processing delay and line memory size is performed, then pipeline execution can be achieved, but productivity decreases due to time-consuming recalculation especially in complex processes
Solution Approach 1:
The patent applies self-service by enabling the compiler to automatically determine processing delay amounts and line memory sizes by analyzing the source program's memory access patterns. This eliminates manual calculation and recalculation tasks, significantly reducing development time and improving productivity especially for complex processes.
Solution Approach 2:
The patent replaces manual mechanical calculation with automated computer-based analysis. The compiler systematically analyzes read/write operations, calculates necessary delays, and generates optimized codes automatically, substituting human manual computation with machine automation to eliminate time-consuming recalculation.
Data Source
AI summary
According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.