Compiler Prespill Phase for Register Pressure Reduction

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Solution Overview

Problem

Existing compilers handle excessive register pressure only during register allocation, limiting the effectiveness of early and late instruction schedulers and restricting code optimization, as they cannot address register spilling until after register allocation.

Innovation Solution

A prespill phase is introduced in the compiler to identify and reduce excessive register pressure by selecting candidate virtual registers and inserting spill and reload instructions before register allocation, allowing for optimized instruction scheduling and simplified register allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If register allocation is performed before instruction scheduling, then register pressure can be managed, but early instruction schedulers cannot optimize spill and reload instructions

Engineering Contradiction:
Improvecode execution efficiencyVSAvoidcompiler phase complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a prespill phase that performs preliminary spill candidate identification and insertion of spill/reload instructions before register allocation and instruction scheduling. This preliminary action allows early instruction schedulers to optimize these instructions later, resolving the contradiction by enabling both register pressure management and instruction optimization.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If spill instructions are inserted during register allocation, then register pressure is reduced, but early instruction schedulers cannot optimize them

Engineering Contradiction:
Improveinstruction optimizationVSAvoidcompilation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The prespill phase performs preliminary insertion of spill and reload instructions with placeholder operations before instruction scheduling. This allows early instruction schedulers to optimize the placement and timing of these instructions without significantly increasing compilation time, as the actual spill operations are determined later during register allocation.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If late instruction scheduling is used, then spill instructions can be optimized, but virtual register to physical register mapping restricts instruction movement

Engineering Contradiction:
Improvespill instruction optimizationVSAvoidinstruction repositioning flexibility
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The prespill phase inserts spill and reload instructions with placeholder operations before register allocation, creating a flexible intermediate representation. This preliminary action allows late instruction schedulers to optimize these instructions while maintaining the ability to move them, as the actual register mappings are not yet fixed at this stage.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If early instruction schedulers focus on minimizing register pressure, then register allocation is simplified, but execution stall minimization is compromised

Engineering Contradiction:
Improveexecution stall minimizationVSAvoidinstruction scheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the instruction scheduling process into early and late phases with distinct objectives. The prespill phase handles preliminary spill instruction insertion, early instruction scheduling focuses on stall minimization, and late instruction scheduling optimizes spill instructions. This segmentation allows each phase to specialize, resolving the contradiction between execution efficiency and scheduling complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8516465B2Register prespill phase in a compiler
Publication Date: 2013.08.20 ORACLE AMERICAN INC
  • US8516465B2 patent drawing
  • US8516465B2 patent drawing
  • US8516465B2 patent drawing

AI summary

The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.