Compiler-Assisted Register File Write Reduction

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Solution Overview

Problem

Partial updates in register files of graphics processing units (GPUs) lead to wasted bandwidth and increased power consumption due to read-modify-write operations, particularly in applications like machine learning where instructions often have operands of different data types, causing performance losses and increased power usage.

Innovation Solution

A compiler-assisted approach that groups instructions causing partial register writes and provides hardware hints to combine outputs for single writes, emulating read-modify-write operations only when necessary, thereby reducing the number of register file writes and improving write bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If partial updates are performed in register files, then byte-level write granularity is achieved, but bandwidth is wasted and power consumption increases

Engineering Contradiction:
Improvebyte-level write granularityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent merges multiple partial write operations into a single consolidated write operation. The register file includes multiple write ports that can simultaneously write to different bytes of the same register, and the control logic combines these writes into one unified write cycle, eliminating redundant read-modify-write sequences and reducing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by detecting multiple write operations targeting the same register before they are executed. The control logic identifies these overlapping writes in advance and prepares a consolidated write operation, preventing the execution of unnecessary read-modify-write cycles and reducing power consumption before the actual write occurs.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If partial updates are performed in register files, then byte-level write granularity is achieved, but bandwidth is wasted

Engineering Contradiction:
Improvebyte-level write granularityVSAvoidwrite bandwidth
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges multiple partial write operations into a single consolidated write operation. The register file includes multiple write ports that can simultaneously write to different bytes of the same register, and the control logic combines these writes into one unified write cycle, eliminating redundant read-modify-write sequences and reducing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by detecting multiple write operations targeting the same register before they are executed. The control logic identifies these overlapping writes in advance and prepares a consolidated write operation, preventing the execution of unnecessary read-modify-write cycles and reducing power consumption before the actual write occurs.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If read-modify-write operations are used, then partial register updates are enabled, but power consumption increases

Engineering Contradiction:
Improvepartial register update capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple partial write operations into a single consolidated write operation. The register file includes multiple write ports that can simultaneously write to different bytes of the same register, and the control logic combines these writes into one unified write cycle, eliminating redundant read-modify-write sequences and reducing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by detecting multiple write operations targeting the same register before they are executed. The control logic identifies these overlapping writes in advance and prepares a consolidated write operation, preventing the execution of unnecessary read-modify-write cycles and reducing power consumption before the actual write occurs.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If multiple write ports are added to register file, then write bandwidth is improved, but device complexity increases

Engineering Contradiction:
Improvewrite bandwidthVSAvoidregister file complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the write operation control into multiple independent write ports, each capable of handling write operations independently. This segmentation allows parallel write operations to different bytes of the same register, improving write bandwidth while keeping each individual write port relatively simple in structure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11900502B2Compiler assisted register file write reduction
Publication Date: 2024.02.13 INTEL CORP
  • US11900502B2 patent drawing
  • US11900502B2 patent drawing
  • US11900502B2 patent drawing

AI summary

Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.