Compiler-Scheduled Compute Slices for Parallel Data Processing
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Solution Overview
Problem
Current computer processing architectures face inefficiencies in handling large and unstructured datasets, leading to increased energy consumption and heat production, while struggling to execute complex tasks such as machine learning and data processing quickly and cost-effectively.
Innovation Solution
A processor-implemented method utilizing a parallel architecture with compiler-scheduled compute slices, where each slice is coupled by barrier register sets, allowing for parallel execution of tasks based on branch prediction logic, enabling efficient data communication and task distribution across multiple compute slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computational resources are used to process large unstructured datasets, then processing capacity is provided, but energy consumption increases and heat is produced
Solution Approach 1:
The computational architecture is segmented into multiple independent compute slices (first compute slice, second compute slice, third compute slice) that can operate in parallel. Each slice processes portions of the dataset independently, enabling distributed computation that improves processing capacity while managing energy consumption across multiple units rather than overloading a single resource
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension to computation. Multiple compute slices execute simultaneously rather than sequentially, effectively moving from one-dimensional sequential operations to multi-dimensional parallel operations, thereby increasing processing capacity without proportionally increasing energy consumption per unit of work
2Speed
If computational resources operate continuously to meet data processing needs, then processing speed is maintained, but heat production increases
Solution Approach 1:
The system divides computational workload across multiple compute slices that can be activated or deactivated independently. This segmentation allows the system to maintain processing speed by distributing work across available slices while reducing heat production by keeping individual slices operational for shorter durations and allowing thermal dissipation between tasks
Solution Approach 2:
The compiler performs preliminary analysis and generates optimized code that pre-determines execution paths and data flow between compute slices. This preliminary compilation phase allows the system to execute processed code efficiently during runtime, maintaining high processing speed while reducing the need for continuous resource operation and associated heat generation
3Productivity
If parallel execution is implemented across multiple compute slices, then processing efficiency improves, but system complexity increases
Solution Approach 1:
Barrier registers serve as intermediary structures between compute slices, providing standardized interfaces for data exchange and synchronization. These barrier registers simplify the complexity of parallel execution by offering a uniform mechanism for inter-slice communication, eliminating the need for complex custom synchronization logic and making the parallel architecture more manageable
Solution Approach 2:
The compute slices are designed as universal, identical units that can execute any portion of the compiled code. This universality reduces architectural complexity by eliminating the need for specialized hardware for different computation types - the same slice architecture handles all computational tasks, simplifying design and maintenance while enabling efficient parallel execution
4Productivity
If data is processed through multiple compute slices with barrier registers, then data throughput increases, but communication overhead increases
Solution Approach 1:
The compiler performs preliminary analysis of data dependencies and execution paths during the compilation phase. It generates optimized code that pre-arranges data flow between compute slices and pre-calculates barrier synchronization points. This preliminary action eliminates the need for runtime dependency checking, reducing communication overhead and time loss while maintaining high data throughput
Solution Approach 2:
The barrier registers provide feedback mechanisms that signal when data is ready for transfer between compute slices. This feedback system enables synchronized parallel execution by automatically coordinating data availability signals between slices, reducing communication overhead through automated synchronization rather than complex inter-slice communication protocols
Data Source
AI summary
Techniques for task processing based on compiler-scheduled compute slices are disclosed. A processing unit comprising compute slices, barrier register sets, a control unit, and a memory system is accessed. Each compute slice includes an execution unit and is coupled to other compute slices by a barrier register set. A first slice task is distributed to a first compute slice. A second slice task is allotted to a second compute slice, based on a branch prediction logic. The second compute slice is coupled to the first by a first barrier register set. Pointers are initialized. A compiled program is executed, beginning at the first compute slice. The second slice task can be executed in parallel while a branch decision is being made. If the branch decision determines that the second slice task is not the next sequential slice task, results from the second compute slice are discarded.