Compiler Scheduling Apparatus for Accelerator Data Transfer
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Solution Overview
Problem
Existing scheduling techniques for compiler devices do not effectively account for the device configuration when generating schedules, leading to increased execution time due to inefficient data access in systems with accelerator chips that have high data transfer costs.
Innovation Solution
A scheduling apparatus that includes at least one processor and memory, capable of generating a schedule by replacing data transfer processes with recomputation processes, thereby optimizing computation order and recomputation points based on the device configuration, particularly for systems with accelerator chips that have high data transfer costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is saved to large memory for later access, then data availability is improved, but execution time increases due to slow memory access
Solution Approach 1:
The patent performs preliminary actions by computing and storing intermediate results in fast memory before they are needed, rather than waiting to retrieve them from slow large memory. This allows the system to have data ready when needed without incurring slow memory access delays during execution.
Solution Approach 2:
The patent creates copies of data in different memory locations or computational units. Instead of accessing the original data in slow large memory, the system maintains copies in fast memory or registers, allowing rapid access without compromising data availability.
2Ease of operation
If data transfer processes are used to access memory, then data access is simplified, but the number of steps and execution time increase
Solution Approach 1:
The patent extracts the data transfer operation from the critical computation path by pre-fetching and caching data before it is needed. This separates the data movement operation from the computation operation, allowing the computation to proceed without waiting for slow memory transfers.
Solution Approach 2:
The patent introduces intermediate storage structures (such as fast memory or register files) that act as mediators between large memory and the computational units. These intermediaries buffer data transfers, allowing computations to proceed with minimal waiting time while maintaining simplified access patterns.
3Ease of manufacture
If general-purpose scheduling is used, then schedule generation is straightforward, but it does not account for device configuration leading to inefficient execution
Solution Approach 1:
The patent applies local quality by tailoring the scheduling strategy to specific device characteristics. Different computational units or memory regions receive customized scheduling treatments based on their local properties (such as speed, capacity, or connectivity), optimizing overall execution efficiency while maintaining manageable complexity.
Data Source
AI summary
A scheduling apparatus includes at least one memory and at least one processor, and the at least one processor is configured to generate a schedule from a state specified based on received information. The generating includes causing the state to transition such that a process of transferring data from a memory is replaced with a recomputation process that obtains the data.