Compiler Shift Insertion for Address Generation Interlock Reduction
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Solution Overview
Problem
Mainframe computer systems, such as IBM's zSeries, experience significant delays due to address generation interlock (AGI) issues, which occur when one instruction updates a register used by another, leading to pipeline stalls, despite existing optimization techniques like induction variable analysis and instruction scheduling.
Innovation Solution
The method involves scanning code blocks from most frequent to least frequent to insert shifts before arithmetic references, after memory uses, and after arithmetic references, determining required shift amounts, and adjusting shifts to match between blocks, thereby reducing AGI delays by minimizing the need for register updates during address generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed in a pipelined manner with multiple instructions at different stages simultaneously, then processing throughput is improved, but address generation interlock delays occur when one instruction updates a register needed by another instruction
Solution Approach 1:
The patent applies preliminary action by performing shift operations on index registers in advance, before they are needed for address generation. The compiler inserts shift instructions that execute ahead of time, so when an address generation instruction needs the shifted index value, it is already available in the register, preventing pipeline stalls caused by address generation interlocks.
2Manufacturing precision
If shift operations are inserted frequently to maintain proper index register values, then address generation accuracy is improved, but the number of instructions and processing overhead increase
Solution Approach 1:
The patent applies local quality by making shift operations local to specific code blocks rather than globally throughout the entire program. The compiler analyzes each basic block individually and inserts shifts only where needed within that block, optimizing for the local address generation requirements without unnecessarily increasing the overall instruction count across the entire program.
Solution Approach 2:
The patent changes the parameter of index register values by inserting shift operations that modify the register contents. The compiler determines the required shift amount and inserts appropriate shift instructions to transform the index register value from its original state to the required state for correct address generation, thereby changing the parameter (register value) to achieve accurate addressing.
3Productivity
If existing optimization techniques like induction variable analysis and loop unrolling are applied, then overall code optimization is improved, but significant AGI delays remain in highly optimized code
Solution Approach 1:
The patent introduces shift operations as an intermediary mechanism between the original index register and the address generation instructions. Rather than directly using the index register value for addressing, the shift operation acts as an intermediary that transforms the index value into the correct form needed for address generation, thereby eliminating the need for address generation interlocks even in highly optimized code where other optimizations have been applied.
Data Source
AI summary
Data processing delay is reduced during data processing, using compiler optimization. Blocks of code are scanned in an order from blocks recurring most often to blocks recurring least often. In an order from blocks recurring most often to block recurring least often, shifts are inserted before arithmetic references, such that a previous use of the arithmetic reference does not require a shift, shifts are inserted after each memory use such that the next use of the memory does not require a shift, and shifts are inserted after each arithmetic reference such that the next use of the arithmetic reference requires no shift. In addition, if there is a mismatch between the last shifted amount of any one block and the required initial shifted amount in any of its successors, shifts are inserted to make up for the mismatch.