Compiler Shim Layer for Hardware Transactional Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware transactional memory (HTM) systems lack compiler support, making it difficult for developers to utilize HTM instructions effectively, which are complex and require assembly coding, thereby hindering easy parallel programming and performance benefits.
Innovation Solution
Providing a compiler with support for software transactional memory (STM) functions and mapping these functions to HTM instructions through a thin software shim layer, leveraging existing STM compiler infrastructure to generate assembly code for transaction boundary demarcation and memory barriers, allowing HTM systems to utilize STM functions implemented directly with HTM instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware transactional memory instructions are used, then parallel programming performance is improved, but device complexity increases due to specialized hardware modifications required
Solution Approach 1:
The patent introduces a software shim layer as an intermediary between the high-level programming language and the hardware transactional memory instructions. This shim layer translates STM functions into HTM instructions, allowing developers to write code using familiar STM semantics while the underlying hardware provides the actual transactional memory support. This resolves the contradiction by maintaining hardware complexity but simplifying the software interface.
Solution Approach 2:
The patent replaces complex hardware-based transactional memory implementation with a software-based approach that leverages existing hardware capabilities. Instead of requiring complete hardware redesign, the system uses software shims to provide transactional memory functionality on top of conventional hardware, substituting mechanical hardware complexity with software abstraction layers.
2Speed
If hardware transactional memory is implemented, then transaction execution speed is improved, but ease of operation deteriorates due to assembly coding requirements
Solution Approach 1:
The software shim layer serves as an intermediary that translates high-level STM function calls into low-level HTM instructions. Developers can write code using intuitive STM syntax while the shim layer handles the complex instruction translation, maintaining both ease of operation and execution speed.
Solution Approach 2:
The patent uses a thin software shim layer that can be easily implemented and discarded once the transactional memory functionality is provided. This lightweight approach avoids the need for complex, long-term hardware modifications while still providing the performance benefits of HTM.
3Ease of manufacture
If software transactional memory is used, then ease of manufacture is improved due to minimal hardware alterations, but productivity deteriorates due to lack of compiler support
Solution Approach 1:
The patent creates a universal shim layer that can work with multiple different HTM instruction sets and hardware implementations. This multi-functional approach allows the same software layer to provide STM functionality across different hardware platforms, improving productivity by enabling compiler support for various HTM systems.
Solution Approach 2:
The patent performs preliminary translation of STM functions into HTM instructions during the compilation process. By preparing the translation mappings in advance through the shim layer, the system enables efficient compiler support for HTM without requiring post-compilation modifications or complex runtime overhead.
Data Source
AI summary
A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.