Compiler-Synthesized Compute Architecture for In-Storage Processing
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Solution Overview
Problem
The CPU-based model of calculation is limited by cache coherence, memory wall, and data movement issues, hindering improved computation performance.
Innovation Solution
Offload computation into data storage space using computational storage or memory, employing data processing units (DPUs) and field-programmable gate array (FPGA) cores, with a compiler synthesizing specialized computational cores and architectures to optimize data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computation is performed using CPU-based model, then general-purpose computing is achieved, but computation performance is limited by cache coherence, memory wall, and data movement issues
Solution Approach 1:
The patent combines storage and computation functions into a unified computational storage device, merging previously separate CPU, memory, and storage components. This integration eliminates the need for data to move between separate processing and storage systems, directly addressing the memory wall and data movement bottlenecks while maintaining general-purpose computing capabilities through the programmable processor array.
Solution Approach 2:
The patent introduces a new architectural dimension by creating a distributed processor array where multiple processing elements are arranged in a two-dimensional grid structure. This spatial dimensionality allows computations to be performed closer to where data is stored in memory arrays, reducing data movement distances and enabling parallel processing that overcomes traditional CPU performance limitations.
2Productivity
If data is moved between persistent memory, DRAM, and CPU cache, then computation can be performed, but latency and processing time increase
Solution Approach 1:
The patent extracts the computation function from the CPU and relocates it directly into the storage device. By taking out the processing capability from the traditional CPU location and embedding it within the computational storage device, data can be processed in-place within the storage medium without requiring movement through DRAM and CPU cache hierarchies, eliminating the time loss associated with data transfer.
Solution Approach 2:
The patent introduces a computational storage device as an intermediary between traditional storage and processing systems. This intermediary component includes embedded processors that can perform computations directly on stored data, acting as a mediator that eliminates the need for data to traverse the entire memory hierarchy from persistent memory through DRAM to CPU cache, thereby reducing latency and processing time.
3Productivity
If computational storage devices are used, then data processing performance is enhanced, but compatibility with existing CPU platforms is reduced
Solution Approach 1:
The patent implements a universal interface and communication protocol that allows the computational storage device to function with multiple different CPU platforms and architectures. The processor array can be programmed to perform various computational tasks, and the device can operate in different modes (autonomous processing, co-processing with CPU, or as enhanced storage), providing multi-functionality that maintains compatibility across different system configurations while delivering enhanced processing performance.
Data Source
AI summary
The present disclosure describes techniques for computation architecture synthesis. Objects may be detected based on source code by a compiler. A type of each object may be identified by the compiler. A plurality of streams each of which corresponds to a particular type of objects among a plurality of types of objects may be defined. A set of operations to be applied to the particular type of objects may be detected. A computational core may be synthesized based on the set of operations. A computational architecture may be synthesized based on the plurality of streams and a plurality of computational cores each of which is associated with at least one of the plurality of streams.