Synchronous Circuit Compiler Maintaining Thread Execution Order
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Solution Overview
Problem
Hardware description languages (HDLs) require extensive code for digital logic circuit modeling, leading to time-consuming design processes and increased error likelihood, especially for software engineers unfamiliar with HDLs, resulting in poor performance and errors in electronic circuits.
Innovation Solution
A language and compiler that generate synchronous digital circuits, maintaining thread execution order through constructs like reorder blocks and balanced pipeline stages, allowing for low-overhead thread synchronization and order-specific operations, making it easier for software engineers to create high-performance circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware description languages (HDLs) are used to model digital logic circuits, then the circuit design can be implemented in hardware, but the number of code lines increases significantly and the design process becomes time-consuming
Solution Approach 1:
The patent uses a high-level programming language that is familiar to software engineers, copying the programming paradigm from software to hardware domain. This allows engineers to write hardware descriptions using conventional programming constructs rather than learning specialized HDL syntax, thereby reducing code lines and development time while maintaining design correctness
Solution Approach 2:
The invention changes the fundamental parameter of programming language paradigm from HDL-specific syntax to high-level imperative programming. This parameter change enables software engineers to leverage their existing knowledge, reducing the learning curve and development time while improving productivity without sacrificing circuit design reliability
2Reliability
If HDLs are used for circuit modeling, then hardware implementation is achieved, but the likelihood of design errors increases
Solution Approach 1:
By copying the well-established high-level programming paradigm from software engineering, the patent eliminates the need for engineers to learn complex HDL-specific constructs. This reduces code complexity and the likelihood of errors while maintaining the ability to implement hardware circuits
Solution Approach 2:
The patent segments the hardware design process into manageable high-level programming constructs that can be composed systematically. This segmentation reduces code complexity by breaking down complex circuit designs into modular, reusable components that are easier to verify and less prone to errors
3Adaptability or versatility
If software engineers use HDLs to create circuit designs, then cross-disciplinary collaboration is enabled, but the performance and correctness of generated circuits deteriorate
Solution Approach 1:
The patent creates a universal programming language that serves both software engineers and hardware implementation requirements. This multi-functional language allows software engineers to write code without specialized HDL training while the compiler ensures correct hardware generation, thereby enabling cross-disciplinary collaboration without sacrificing circuit performance or correctness
4Productivity
If thread execution order is not maintained in pipelined circuits, then throughput is improved, but synchronization overhead increases
Solution Approach 1:
The patent applies preliminary action by maintaining thread execution order at the pipeline stage level before outputs are generated. This preliminary ordering simplifies subsequent synchronization operations, reducing the overhead required for thread synchronization while maintaining high throughput through efficient pipeline utilization
Data Source
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AI summary
A multi-threaded programming language and compiler generates synchronous digital circuits that maintain thread execution order by generating pipelines with code paths that have the same number of stages. The compiler balances related code paths within a pipeline by adding additional stages to a code path that has fewer stages. Programming constructs that, by design, allow thread execution to be re-ordered, may be placed in a reorder block construct that releases threads in the order they entered the programming construct. First-in-first-out (FIFO) queues pass local variables between pipelines. Local variables are popped from FIFOs in the order they were pushed, preserving thread execution order across pipelines.