Compiler Vector Load and Shift for Program Speed
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Solution Overview
Problem
Existing compile devices, such as those described in Patent Literature 1, face inefficiencies in optimizing source programs for vector computers, leading to insufficient speed improvements due to deficiencies in arithmetic operations and the need for additional instructions to compensate for lacking elements.
Innovation Solution
A compile device and method that convert primitive programs with arithmetic calculations involving array elements into object code using vector load and shift instructions, optimizing resource utilization by packing data into vector registers and generating instructions to perform arithmetic operations efficiently, thereby eliminating the need for additional instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the compiler converts adjacent memory access instructions into one memory access instruction with data sliding, then memory access efficiency is improved, but arithmetic operation elements become deficient requiring additional instructions
Solution Approach 1:
The invention changes the data organization dimension by packing multiple (1/2)k word data units into a single 1-word vector register. Instead of handling each (1/2)k word separately, the compiler loads data in packed format where one vector register contains multiple data elements, enabling simultaneous access to multiple array elements (A[i], A[i+1], A[i+2k]) without requiring additional instructions for element extraction or alignment.
Solution Approach 2:
The invention changes the data width parameter from (1/2)k word to 1-word packing. By treating multiple smaller data units as a single wider data type in vector registers, the compiler can perform arithmetic operations on all required elements (A[i], A[i+1], A[i+2k]) simultaneously using standard vector instructions, eliminating the need for additional instructions to compensate for deficient elements.
2Reliability
If the compiler generates additional vector or scalar instructions to compensate for deficient elements, then arithmetic operation completeness is improved, but program execution speed decreases
Solution Approach 1:
The invention performs preliminary action by pre-packing multiple data units into vector registers in the load phase. Before arithmetic operations are executed, all necessary elements (A[i], A[i+1], A[i+2k]) are already available in properly aligned vector registers, eliminating the need for compensatory instructions during the computation phase and maintaining high execution speed.
Solution Approach 2:
The invention makes vector registers multi-functional by using them to store multiple different data types ((1/2)k word units) in a unified packed format. The same vector register infrastructure that handles standard 1-word data is also used to efficiently store and operate on multiple smaller data units, eliminating the need for specialized instructions for different data width scenarios.
Data Source
AI summary
A vector load instruction generating unit of a compile device generates an instruction to load a “first group of data units”, which is used as an element A[i] in iterative calculation processing, from a memory into a first vector register in a state of being packed in units of 1-word. Each data unit is (1/2)k word. The vector load instruction generating unit generates an instruction to load a second group of data units, which is used as an element [i+2k] into a second vector register. A vector shift double instruction generating unit generates an instruction to cause a part of a data string, which is obtained by shifting data of the first vector Register and the second register by (1/2)k word as a series of data string, to be stored in a third vector register in a state of being packed in units of 1-word.