Compiler Vector Instruction Scheduling to Avoid Store Fetch Interlock
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Solution Overview
Problem
The occurrence of Store Fetch Interlock (SFI) in microprocessors, which leads to increased execution time due to in-order execution of consecutive store and load instructions, especially when the vector length increases, causing architectural-dependent SFI that does not require original SFI conditions.
Innovation Solution
A compiler program optimizes vector instructions by unrolling and scheduling loop operations to avoid architectural-dependent SFI, using loop unrolling and instruction reordering to execute store and load instructions out-of-order, thereby reducing execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the vector length of the microprocessor is increased to process more array elements in parallel, then the processing capacity and productivity are improved, but the frequency of occurrence of architectural-dependent Store Fetch Interlock (SFI) increases, leading to longer execution time
Solution Approach 1:
The compiler performs preliminary analysis of the mask registers associated with vector store and load instructions before code generation. By examining the mask bit patterns in advance, the compiler can identify potential architectural-dependent SFI conditions and restructure the code to avoid them, allowing the processor to execute instructions out-of-order without unnecessary interlocks.
Solution Approach 2:
The invention changes the approach from executing instructions in the original program order to reordering them based on mask register analysis. By analyzing the mask bits that control which elements are accessed, the compiler can determine that certain store and load instructions can be executed in different orders without affecting correctness, thus avoiding architectural-dependent SFI and reducing execution time.
2Reliability
If the microprocessor executes consecutive store and load instructions in-order based on architectural-dependent SFI, then the correctness of memory access is ensured, but the execution period becomes longer than necessary
Solution Approach 1:
The compiler acts as an intermediary between the program logic and the processor execution. It inserts scheduling instructions or reorders instructions based on mask register analysis, allowing the processor to execute store and load instructions out-of-order when safe to do so, while still ensuring correctness. This intermediary layer enables the processor to bypass unnecessary architectural-dependent SFI interlocks.
Solution Approach 2:
The compiler performs preliminary analysis of mask registers to determine which elements will be accessed by store and load instructions. By knowing in advance which memory locations will be modified and which will be read, the compiler can restructure the instruction sequence to allow out-of-order execution without compromising correctness, thus reducing the execution period.
3Productivity
If the vector length array elements are increased to cover a larger area of memory addresses, then the processing throughput is improved, but the area of memory addresses that may cause architectural-dependent SFI is extended, increasing the frequency of SFI occurrence
Solution Approach 1:
The invention changes the execution order parameter based on mask register analysis. By examining which mask bits are set to TRUE or FALSE, the compiler can determine that even though a large area of memory addresses is accessed, not all addresses within that area are actually accessed. This allows the compiler to reorder instructions to avoid architectural-dependent SFI while maintaining the benefits of processing a large number of elements.
Data Source
AI summary
A compiler program causes a computer to execute optimization processing for an optimization target program. The optimization target program includes a loop including a vector store instruction and a vector load instruction for an array variable. The optimization processing includes (1) unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, and (2) scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.