Compiler Vectorization for Adjacent Data Access

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Solution Overview

Problem

Existing compiling methods for vector computers are inefficient due to increased vector load instruction executions and redundant memory accesses when processing adjacent data, leading to slowed program performance.

Innovation Solution

A compiling device and method that analyzes loops for vectorization potential and generates vector load, shift, computation, and store instructions to efficiently load and process adjacent data without redundant memory accesses, replacing vector load instructions with vector element shift instructions to reduce memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a vector load instruction is issued to each array element, then data can be loaded into the vector register, but the number of vector load instruction executions increases and redundant memory accesses occur

Engineering Contradiction:
Improvenumber of vector load instructionsVSAvoidprogram execution speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies preliminary action by loading a continuous range of data elements into the vector register in advance, rather than loading individual elements as needed. This allows subsequent computations to access already-loaded data, reducing the total number of vector load instructions executed and eliminating redundant memory accesses that would otherwise occur when processing adjacent data elements.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating multiple views or interpretations of the same loaded vector data through shifting operations. Instead of loading separate data for each computation, the same vector register contents are copied and shifted to generate different data sequences, thereby reducing memory access while maintaining computational functionality.

Inventive Principle:
Principle #26Copying

2Productivity

If data is shifted to access adjacent elements, then memory access can be reduced, but scalar computation or mask handling is required which reduces operation efficiency

Engineering Contradiction:
Improvememory access efficiencyVSAvoidcomputation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical approach of scalar computation or mask handling with a more efficient vectorized shifting mechanism. Instead of using scalar loops or complex mask operations to handle adjacent data access, the invention uses vector shift instructions that operate on entire data sets simultaneously, reducing both computation complexity and maintaining high productivity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If overlapping elements are loaded between vector load instructions, then data availability is improved, but program speed is reduced due to redundant loading

Engineering Contradiction:
Improvedata availabilityVSAvoidprogram execution speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies discarding and recovering by allowing overlapping data elements to be loaded into the vector register, where they initially serve one computation and then are reused (recovered) for subsequent computations. This eliminates the need to discard and reload the same data, improving data availability while maintaining program speed by avoiding redundant memory access operations.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20240053969A1Compiling device, compiling method, and compiling program recording medium
Publication Date: 2024.02.15 NEC CORP
  • US20240053969A1 patent drawing
  • US20240053969A1 patent drawing
  • US20240053969A1 patent drawing

AI summary

Provided are a compiling device, a compiling method, and a compiling program with which the speed of a program can be increased when a loop in a program includes an access to adjacent data. The compiling device includes: a loop analysis unit for determining whether vectorization of a loop in a source program is possible when an access to adjacent data is included in the loop; and a vectorization execution unit for generating an instruction for reading elements required for computation from a memory to a vector register when access to the adjacent data is included and the vectorization of the loop is possible.