Complementary MOS Amplifier Biasing for Constant Transconductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Amplifiers fabricated with deep sub-micron CMOS processes face challenges in achieving good linearity and reliability due to transistor nonlinearity, which is exacerbated by shrinking physical dimensions.
Innovation Solution
A complementary amplifier design utilizing an N-channel metal oxide semiconductor (NMOS) transistor and a P-channel metal oxide semiconductor (PMOS) transistor in a stacked configuration, with separate bias voltages and carefully selected dimensions to maintain constant total input capacitance and transconductance, thereby improving linearity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sub-micron CMOS fabrication processes are used to reduce cost and improve integration, then manufacturing cost decreases and integration improves, but transistor linearity deteriorates
Solution Approach 1:
The amplifier is segmented into two separate transistors (NMOS and PMOS) operating in complementary fashion. Each transistor handles a portion of the signal range, with the NMOS active during negative half-cycles and PMOS during positive half-cycles, thereby maintaining linearity across the full signal range while using standard sub-micron CMOS processes
Solution Approach 2:
The invention uses a composite transistor structure combining NMOS and PMOS devices in a stacked configuration. This composite approach leverages the complementary characteristics of the two transistor types to achieve linear operation, where the combined transfer function of the complementary pair provides improved linearity compared to single-transistor designs in sub-micron CMOS
2Productivity
If physical dimensions of transistors are shrunk to improve CMOS fabrication technology, then integration improves, but reliability requirements become more demanding and linearity deteriorates
Solution Approach 1:
By dividing the amplification function across two transistors operating in complementary fashion, each transistor can be designed with optimized dimensions for the available process node. The segmentation allows each device to operate in a more favorable region, mitigating the linearity degradation inherent in scaled transistors
Solution Approach 2:
The invention changes the operating parameters by using separate bias voltages for the NMOS and PMOS transistors. This allows independent optimization of each transistor's operating point to maintain linearity. The bias voltages are specifically chosen to ensure that the transistors operate in regions where their transfer characteristics provide the best linearity for the given process technology
3Reliability
If separate bias voltages are applied to NMOS and PMOS transistors to maintain constant transconductance, then linearity improves, but device complexity increases
Solution Approach 1:
The bias circuit is designed to automatically generate the appropriate separate bias voltages for the NMOS and PMOS transistors based on their operating conditions. The circuit self-adjusts to maintain constant total transconductance without requiring external control, thereby achieving improved linearity while minimizing the increase in device complexity
Data Source
AI summary
A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.