Bidirectional Shift Register Using Complementary Clocks for Stable Output
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Solution Overview
Problem
Conventional bidirectional shift registers exhibit high power consumption due to inverter structures and clock coupling effects, leading to unstable output waveforms in display applications.
Innovation Solution
A shift register design featuring a series connection of stages with specific transistor and capacitor configurations, utilizing MOS thin film transistors and eliminating inverter structures to reduce power consumption and stabilize output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inverter structures are used in conventional bidirectional shift registers, then the circuit can provide signal inversion and driving capability, but power consumption increases and output waveform stability deteriorates
Solution Approach 1:
The patent removes the inverter structure from the shift register circuit. Specifically, the inverter that was connected to the gate line drive unit is eliminated, and the transistor Q1 is reconfigured to directly supply clock signals without requiring inversion. This extraction of the harmful inverter component resolves the contradiction by eliminating the source of high power consumption and waveform instability while maintaining the necessary signal driving capability through alternative circuit configuration.
Solution Approach 2:
Instead of using an inverter to achieve signal inversion, the patent employs a complementary clock signal approach. The second clock terminal CK2 receives an inverted clock signal directly from the external source, and the circuit uses this inverted signal in conjunction with the non-inverted signal from CK1 to achieve bidirectional shifting. This inverts the approach from active inversion (using an inverter circuit) to passive inversion (using externally provided complementary clocks).
2Reliability
If clock coupling effects are present in conventional shift registers, then the circuit can operate with simple clocking, but output waveform stability deteriorates
Solution Approach 1:
The patent introduces separate clock terminal circuits as intermediaries between the external clock sources and the internal shift register stages. Each clock terminal (CK1 and CK2) has dedicated transistors (Q1 and Q5) that act as mediators to buffer and isolate the clock signals. This intermediary structure prevents direct clock coupling between adjacent stages while maintaining stable output waveforms, resolving the contradiction by adding controlled complexity to eliminate harmful coupling effects.
3Adaptability or versatility
If conventional bidirectional shift register designs are used, then the circuit can achieve bidirectional shifting capability, but power consumption increases due to additional transistors and inverter structures
Solution Approach 1:
The patent merges the clock signal supply function and the shifting control function into a unified circuit structure. The same transistors (Q1-Q6) that control the bidirectional shifting also supply the clock signals to the D inputs of the flip-flops. This merging eliminates the need for separate inverter structures and redundant transistor configurations, achieving bidirectional capability with reduced power consumption by consolidating functions rather than duplicating components.
Data Source
AI summary
A shift register comprising a plurality of shift register stages {SN}, N=1, 2, . . . , M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N−1)-th shift register stage SN−1 for receiving an output signal OUT(N−1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.