Complementary Decoder Circuitry for Memory Signal Latency
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Solution Overview
Problem
Memory devices face latency issues due to decoder circuits, which introduce delays in signal propagation, hindering the increase in operating speed and storage capacity demanded by modern applications.
Innovation Solution
The implementation of complementary decoder circuitry, where transistors are configured to be in high or low impedance states based on specific logic levels, reducing latency by optimizing signal propagation through the use of n-type and p-type field effect transistors in decoder circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoder circuits are used in memory devices, then memory devices can perform selection and deselection of memory cells, but signal latency increases and operating speed decreases
Solution Approach 1:
The patent applies complementary transistor configurations that dynamically switch between active and high-impedance states based on input signals. The first transistor (n-type) and second transistor (p-type) are configured to be complementary, meaning when one is active the other is in high-impedance state and vice versa. This dynamic switching reduces signal latency by ensuring that only one transistor conducts at a time, eliminating the need for signals to propagate through multiple active transistor levels during selection operations.
Solution Approach 2:
The patent changes the impedance parameter of the transistors based on their operational state. By configuring transistors to switch between low impedance (active) and high impedance (inactive) states, the circuit optimizes signal propagation speed. The complementary configuration ensures that during selection, the path has minimal impedance, while during deselection, both transistors can be in high-impedance state, reducing signal latency and improving operating speed.
2Productivity
If multiple levels of decoder circuits are implemented, then memory device capacity increases, but cumulative signal delay increases
Solution Approach 1:
The complementary transistor configuration enables dynamic control of signal paths through multiple decoder levels. By using n-type and p-type transistors in complementary pairs, each decoder level can quickly transition between selection and deselection states, reducing the cumulative delay that would otherwise accumulate across multiple decoder stages. The high-impedance state capability allows rapid disconnection of signal paths.
Solution Approach 2:
The patent segments the decoder function into complementary transistor pairs that operate independently but coordinate their states. This segmentation allows each transistor pair to handle selection/deselection locally, preventing signal propagation delays from accumulating across the entire decoder chain. The modular complementary structure enables parallel operation across multiple decoder levels.
Data Source
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AI summary
Apparatus providing decoding for memory devices and methods of operating memory devices using such apparatus. The apparatus include a first transistor having a control gate coupled to a first input node, wherein when the first transistor is configured to a low impedance state the first transistor couples a portion of a memory array to sense circuitry. The apparatus further include a second transistor having a control gate coupled to a logic gate combining a signal of the first input node and a signal of a second input node, wherein when the second transistor is configured to a low impedance state the second transistor couples a portion of the memory array to program circuitry. The first transistor and the second transistor comprise different types of transistors.