Integrated Assemblies with Complementary Digit-Line Shielding
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Solution Overview
Problem
Performance of memory arrays is degraded by cross-talk between neighboring digit-lines, and there is a need for a memory architecture that reduces this cross-talk while maintaining a small footprint to conserve semiconductor real estate.
Innovation Solution
The implementation of integrated assemblies with true and complementary digit-lines that are coupled through sense-amplifier-circuitry, where the complementary digit-lines provide shielding between the true digit-lines in a folded architecture, reducing cross-talk and allowing for efficient use of semiconductor space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional memory array architecture with closely spaced digit-lines is used, then semiconductor real estate is conserved (small footprint), but cross-talk between neighboring digit-lines increases degrading performance
Solution Approach 1:
The patent introduces complementary digit-lines as intermediary elements positioned between true digit-lines. These complementary digit-lines act as mediators that provide electrostatic shielding, reducing the harmful electric field coupling (cross-talk) between adjacent true digit-lines while allowing the memory array to maintain a compact footprint.
Solution Approach 2:
The patent adds a new dimension to the digit-line arrangement by introducing a second set of digit-lines (complementary digit-lines) that operate in parallel with the traditional true digit-lines. This dimensional expansion creates a folded architecture where true and complementary digit-lines alternate, providing shielding without increasing the lateral footprint of the memory array.
2Object-affected harmful factors
If complementary digit-lines are added for shielding, then cross-talk is reduced, but device complexity increases
Solution Approach 1:
The complementary digit-lines serve multiple functions simultaneously: they provide electrostatic shielding between true digit-lines, acts as reference lines for differential signaling, and enable folded architecture for improved signal integrity. This multi-functionality reduces the need for separate dedicated shielding structures, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent merges the functions of signal transmission and electrostatic shielding by combining true digit-lines with complementary digit-lines in a folded architecture. Instead of having separate signal lines and dedicated shielding structures, the complementary digit-lines are integrated into the signaling path itself, reducing the total number of discrete components and interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces cross-talk between neighboring digit-lines, enhances signal-to-noise ratio, and enables higher density and performance of memory arrays, including faster reading and better signal sensing, while conserving valuable semiconductor real estate.
Implementation Method 1
the complementary digit-lines may be coupled with a reference-voltage-source and may provide shielding between the true digit-lines in folded architecture
Data Source
AI summary
Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4F2 layout.