Complementary Driver Circuit for Balanced True-Complement Delays
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Solution Overview
Problem
Standard complementary and differential driver designs introduce delay differences between true and complement phases due to extra inversion, leading to signal distortion, increased deterministic jitter, and asymmetry that is not balanced across varying process, voltage, temperature, and input slew rate conditions.
Innovation Solution
A circuit topology that uses XOR gates and D flip-flops to ensure equal delays between true and complement phases by triggering both signals from a common clock pulse, eliminating the intrinsic delay difference and maintaining symmetry through symmetrically balanced delay paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an inverter is added to generate the complementary phase input signal, then the complementary phase is provided, but a delay difference is introduced that distorts the output signal cross-point and increases deterministic jitter
Solution Approach 1:
The patent applies asymmetry by making the delay paths for true and complement phases symmetric through careful design. Instead of having asymmetric delay paths (one with inverter, one without), the invention creates symmetric paths where both true and complement signals experience equal total delay, eliminating the delay skew caused by the inverter in conventional designs
Solution Approach 2:
The patent changes the delay parameters of the delay devices to achieve equal total delay for both true and complement phases. By adjusting the delay values of delay devices in each path, the invention compensates for the inverter delay and achieves symmetric delay characteristics across varying process, voltage, and temperature conditions
2Manufacturing precision
If extra load is added to slow down the delay for the path with fewer inversions, then the delay can be balanced for a particular set of conditions, but the circuit will not remain in balance for all process, temperature, voltage, and input slew rate conditions
Solution Approach 1:
The patent applies dynamics by using delay devices whose delay characteristics can be adjusted or adapted to different operating conditions. The delay paths are designed to maintain symmetry across varying process, voltage, temperature, and input slew rate conditions, making the delay balance dynamic rather than fixed for a single condition set
Solution Approach 2:
The invention achieves universal delay balance that works across multiple operating conditions (process, voltage, temperature, input slew rate) rather than being optimized for a single condition. The symmetric delay path design provides multi-functional performance that maintains delay equality throughout various operational scenarios
3Speed
If inverters are increased in size to speed up the longer delay path, then that path's delay is reduced, but the circuit complexity increases and relies on accurate predictability of parasitic resistance and capacitance
Solution Approach 1:
The patent segments the delay path into multiple delay devices rather than relying on a single inverter size adjustment. By dividing the delay path into separate delay devices with controllable delay characteristics, the invention achieves delay balancing without increasing inverter size, thereby reducing device complexity and avoiding reliance on accurate parasitic prediction
Data Source
AI summary
A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.