Complementary Envelope Detector for Low-Delay RF Envelope Tracking
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Solution Overview
Problem
Existing envelope tracking (ET) technologies for RF front-end circuits with multiple power amplifiers face challenges in efficiently tracking the time-variant power envelope of RF signals, leading to suboptimal power amplifier efficiency.
Innovation Solution
The use of a complementary envelope detector circuit featuring two pairs of mirrored transistors, which provide a differential output envelope signal to the ET integrated circuit, helping to improve the tracking of RF signal power envelopes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional envelope tracking technologies are used for RF front-end circuits with multiple power amplifiers, then the system can operate with multiple amplifiers, but the tracking of time-variant power envelope is suboptimal leading to reduced power amplifier efficiency
Solution Approach 1:
The envelope detector is divided into two separate transistor pairs (first and second transistor pairs), each handling different aspects of the envelope detection. This segmentation allows each pair to be optimized for specific functions, improving overall tracking accuracy and power amplifier efficiency while maintaining system reliability.
Solution Approach 2:
The patent employs complementary transistor pairs (nFETs and pFETs) with different electrical characteristics to detect the envelope signal. By changing the transistor type parameters and configuring them in complementary pairs, the system achieves better linearity and accuracy in envelope tracking, directly improving power amplifier efficiency without sacrificing reliability.
2Use of energy by moving object
If envelope tracking is implemented to improve power amplifier efficiency, then energy consumption is reduced, but time delay increases and carrier leakage occurs
Solution Approach 1:
The complementary transistor pairs are configured to preemptively track the RF signal envelope through direct coupling and fast response characteristics. This preliminary action allows the envelope detector to anticipate and respond to power variations before they significantly impact amplifier efficiency, reducing time delay while maintaining energy savings.
Solution Approach 2:
The envelope detector uses a composite structure combining nFET and pFET transistor pairs with complementary characteristics. This composite configuration balances the electrical properties to minimize time delay and carrier leakage while preserving the energy efficiency benefits of envelope tracking, achieving a optimal trade-off among multiple competing parameters.
3Device complexity
If simple envelope detection is used, then device complexity is reduced, but second-order harmonics are not filtered and linearity deteriorates
Solution Approach 1:
The patent converts the potentially harmful second-order harmonics generated by the envelope detection process into useful information. The complementary transistor pair configuration inherently suppresses even-order harmonics while the differential output structure further rejects these harmonics, transforming what would be distortion into a cleaner signal without adding significant complexity.
Solution Approach 2:
The envelope detector implements local quality optimization by using complementary transistor pairs with specific electrical characteristics tailored for harmonic suppression. The nFET and pFET pairs are configured with optimized dimensions and biasing to locally minimize second-order harmonics at the detection stage, improving linearity without requiring complex global filtering structures.
Data Source
AI summary
A complementary envelope detector contemplates using two pair of mirrored transistors to provide a differential output envelope signal to an associated envelope tracking integrated circuit (ETIC) that supplies control voltages to an array of power amplifiers. While bipolar junction transistors (BJTs) may be used, other exemplary aspects use field effect transistors (FETs). In an exemplary aspect, a first pair are negative channel FETs (nFETs) and a second pair are positive channel FETs (pFETs).