Complementary FET Channels With Oxide Barriers and SiGe Mobility
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Solution Overview
Problem
CFET technology faces challenges such as negative bias temperature instability (NBTI) due to germanium diffusion in the silicon channel during high thermal budget processes, affecting NMOS devices, and PMOS devices lacking a mobility booster, resulting in performance gaps compared to NMOS devices.
Innovation Solution
A method of manufacturing CFETs involves removing nanosheet release layers from NMOS transistors to form openings, depositing oxide layers, and using a silicon germanium channel to boost PMOS performance by preventing germanium diffusion and improving NBTI through controlled annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high thermal budget processes such as epitaxial process are used, then device fabrication is enabled, but germanium diffusion into silicon channel occurs causing NBTI in NMOS devices
Solution Approach 1:
An oxide layer is deposited as an intermediary barrier between the germanium source and the silicon channel. This oxide layer acts as a diffusion barrier that prevents germanium atoms from migrating into the silicon channel during thermal processes, thereby eliminating NBTI effects while allowing the thermal budget process to proceed for device fabrication.
Solution Approach 2:
The harmful germanium diffusion path is extracted and blocked by introducing the oxide layer. The oxide layer is placed specifically at the interface where germanium would otherwise diffuse into the silicon channel, removing the harmful diffusion mechanism while preserving the beneficial thermal processing capability.
2Productivity
If PMOS device is fabricated with standard structure, then device integration is achieved, but mobility booster is missing resulting in performance gap compared to NMOS
Solution Approach 1:
The PMOS device structure is modified locally by introducing a silicon germanium channel region specifically where needed to boost carrier mobility. This local modification provides the mobility booster function in the PMOS device without requiring changes to the entire device structure or the NMOS device, thereby maintaining integration while improving performance.
Solution Approach 2:
The PMOS channel is constructed using composite silicon germanium material instead of pure silicon. This composite material combines the benefits of silicon (compatibility with existing processes) with germanium (higher carrier mobility), providing the needed performance boost for PMOS devices while maintaining integration with the existing CFET structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances CFET performance by preventing germanium diffusion in NMOS devices and boosting PMOS mobility, thereby improving overall device stability and performance.
Implementation Method 1
depositing a plurality of oxide layers in each of the plurality of openings... preventing germanium diffusion in NMOS devices
Implementation Method 2
improving NBTI through controlled annealing processes
Data Source
AI summary
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.