Complementary FET Source/Drain Contact Layout for Lower Parasitic Resistance
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration density of electronic components increases, leading to challenges such as increased parasitic resistance in nanostructure-FETs, which affects their performance.
Innovation Solution
Forming source/drain contacts of metal in larger volumes within the source/drain recesses, replacing epitaxial regions, to decrease parasitic resistance and improve performance by using a metal with lower resistance than doped semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic resistance in nanostructure-FETs increases
Solution Approach 1:
The patent changes the material parameter of the source/drain contacts from doped semiconductor material to metal material. This parameter change fundamentally alters the electrical resistance characteristic, providing low resistance contact regions that do not scale with feature size reduction, thereby resolving the parasitic resistance issue while maintaining high integration density
Solution Approach 2:
The patent creates a composite structure where metal contact regions are integrated with doped semiconductor source/drain regions. The metal portions provide low resistance pathways while the semiconductor portions maintain device functionality, forming a composite material system that simultaneously addresses both integration density and parasitic resistance requirements
Data Source
AI summary
In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.


