Complementary FET Integration with GaAs HBT Using Etch Stop Layers

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Solution Overview

Problem

Previous attempts to integrate a p-type Field Effect Transistor (FET) with a Gallium Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) have only resulted in n-type FET devices, limiting the design flexibility and operational capabilities of BiFET power amplifiers.

Innovation Solution

A semiconductor structure is developed that includes a p-type HBT with a collector layer and a p-type FET, along with an n-type FET, integrated on a common substrate, using indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP) etch stop layers to achieve complementary FET devices, enabling the formation of high power BiFET amplifiers that can operate at lower reference voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If p-type FET is integrated with GaAs HBT, then complementary FET devices are achieved, but manufacturing complexity increases due to additional etch stop layer requirements

Engineering Contradiction:
Improvecomplementary FET devicesVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

An etch stop layer is introduced as an intermediary element between the HBT collector layer and the FET channel region. This etch stop layer facilitates selective etching processes during fabrication, enabling the formation of p-type FETs with appropriate doping profiles while managing the complexity of integrating multiple device types in a single structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9859173B2Methodologies related to structures having HBT and FET
Publication Date: 2018.01.02 SKYWORKS SOLUTIONS INC
  • US9859173B2 patent drawing
  • US9859173B2 patent drawing
  • US9859173B2 patent drawing

AI summary

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.