Complementary Transistor Gate Stacks for Threshold Voltage Tuning
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, reducing minimum feature sizes poses challenges in achieving desired threshold voltages and reliability, particularly in FinFETs and other transistor types, due to limitations in adjusting interfacial and high-k dielectric layer thicknesses and dopant concentrations.
Innovation Solution
The method involves forming transistors with varying interfacial and high-k dielectric layer thicknesses and dopant concentrations to adjust threshold voltages, using processes such as oxidation, doping, and deposition to create tailored gate stacks for n-type and p-type transistors, allowing for different threshold voltages and improved time-dependent dielectric breakdown performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but achieving desired threshold voltages and reliability becomes more difficult
Solution Approach 1:
The patent applies local quality by forming different interfacial layer thicknesses in different transistor regions. Specifically, a first interfacial layer with a first thickness is formed in a first transistor region, while a second interfacial layer with a second thickness is formed in a second transistor region. This allows each region to have optimized electrical characteristics tailored to its specific device requirements, enabling precise threshold voltage control across transistors with varying channel lengths and maintaining reliability despite reduced minimum feature sizes.
2Manufacturing precision
If interfacial layer thicknesses are adjusted to control threshold voltages, then threshold voltage tuning is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the interfacial layers with different thicknesses before the high-k dielectric layer deposition. The method involves forming a first interfacial layer, then depositing a first high-k dielectric layer over it, followed by forming a second interfacial layer, and finally depositing a second high-k dielectric layer. This sequential preliminary formation of interfacial layers with controlled thicknesses enables precise threshold voltage tuning to be built into the structure early in the manufacturing process, simplifying subsequent fabrication steps.
3Reliability
If dopant concentrations are varied to adjust threshold voltages, then electrical performance is improved, but process complexity increases
Solution Approach 1:
The patent merges the interfacial layer formation and doping steps into a unified process sequence. The method forms interfacial layers with different thicknesses and incorporates dopant introduction during the interfacial layer formation process itself, rather than requiring separate doping steps. This merging of functions allows dopant concentrations to be varied to adjust threshold voltages while reducing overall process complexity, as the doping is integrated into the existing interfacial layer formation workflow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise adjustment of threshold voltages and enhances the reliability and performance of transistors by optimizing interfacial and high-k dielectric layers, addressing the challenges of integration density and component performance.
Implementation Method 1
The interfacial layers may be doped with a same dopant or different dopants, and to a same dopant concentration or different dopant concentrations
Implementation Method 2
using processes such as oxidation, doping, and deposition to create tailored gate stacks
Data Source
AI summary
A method includes forming a first gate stack including forming a first interfacial layer over a first semiconductor region, wherein the first interfacial layer has a first thickness; and forming a first high-k dielectric layer over the first interfacial layer, wherein the high-k dielectric layer has a second thickness. The method further includes forming a second gate stack including forming a second interfacial layer over a second semiconductor region, wherein the second interfacial layer has a third thickness; and forming a second high-k dielectric layer over the second interfacial layer, wherein the second high-k dielectric layer has a fourth thickness. The thicknesses, dopants, and doping concentrations of the first interfacial layer and the second interfacial layer may be different from each other. The thicknesses, dopants, and doping concentrations of the first high-k dielectric layer and the second high-k dielectric layer may be different from each other.