Complementary Gate Driver On Array Circuit Design

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Solution Overview

Problem

Existing Gate Driver on Array (GOA) circuits for panel displays require a large number of thin film transistors and metal lines, which increases the dimension and manufacturing cost, and is not suitable for narrow frame or non-frame panel displays due to the complexity and susceptibility to dust contamination.

Innovation Solution

A complementary gate driver on array circuit design that reduces the number of thin film transistors and metal lines by optimizing the pull-down holding circuit module, allowing for a more compact and efficient GOA circuit structure, with a reduced dimension and improved signal transmission between levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional GOA circuit design is used, then the gate driving function is achieved, but the circuit dimension and manufacturing cost increase due to large number of TFTs and metal lines

Engineering Contradiction:
Improvegate driving functionVSAvoidcircuit dimension
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the pull-up holding circuit and pull-down holding circuit into a single integrated holding circuit module. The shared components (TFTs T3-T7, capacitors C1-C2) are combined into one unified structure that performs both pull-up and pull-down holding functions, reducing the total component count and circuit dimension while maintaining the necessary gate driving functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The holding circuit is designed with multi-functional capability where the same circuit structure and components serve dual purposes: the pull-up holding circuit maintains high voltage levels during charge periods, while the pull-down holding circuit maintains low voltage levels during discharge periods. This multi-functionality reduces overall circuit complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If traditional GOA circuit design is used, then the gate driving function is achieved, but manufacturing yield decreases due to susceptibility to dust contamination

Engineering Contradiction:
Improvegate driving functionVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By combining multiple holding circuits into a single integrated module with shared components, the patent reduces the total number of discrete components that could potentially be contaminated by dust during manufacturing. The compact integrated structure minimizes exposure areas and reduces the probability of dust-related defects.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If traditional GOA circuit design is used, then the gate driving function is achieved, but threshold voltage drift influence increases

Engineering Contradiction:
Improvegate driving functionVSAvoidthreshold voltage stability
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The holding circuits continuously monitor and maintain the voltage levels at gate signal points Q(n) and Q(n+2). By providing active holding functionality that counteracts voltage drift, the circuit incorporates a form of feedback mechanism that stabilizes threshold voltages and compensates for drift over time, improving manufacturing precision.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9934749B2Complementary gate driver on array circuit employed for panel display
Publication Date: 2018.04.03 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US9934749B2 patent drawing
  • US9934749B2 patent drawing
  • US9934749B2 patent drawing

AI summary

A complementary gate driver on array circuit employed for panel display includes a plurality of GOA units that are cascade connected, in which an nth GOA unit controls charge to an nth horizontal scanning line G(n) in a display area and includes a pull-up circuit module, a pull-down circuit module, a pull-down holding circuit module, a pull-up controlling circuit module, a pull-down circuit module of an nth gate signal point Q(n), and a bootstrap capacitor. The pull-up circuit module, the pull-down circuit module, the pull-down holding circuit module, the pull-down circuit module of the nth gate signal point Q(n), and the bootstrap capacitor are respectively coupled to the nth gate signal point Q(n) and the nth horizontal scanning line G(n), and the pull-up controlling circuit module is coupled to the nth horizontal scanning line G(n).