Complementary LNA Calibration for Second-Order Distortion Cancellation
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Solution Overview
Problem
Low noise amplifiers (LNAs) in mobile devices face challenges in reducing noise figure and power consumption while effectively mitigating second-order harmonic interference from surrounding electronic sources, which degrades signal quality and increases power consumption.
Innovation Solution
A complementary LNA design with automated calibration through active device switching and the strategic addition of coupled inductors and capacitors to enhance second-order intercept points, gain, and noise figure, reducing even-order harmonic interference and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional LNA design is used, then power consumption is reduced, but second-order harmonic interference is not effectively mitigated
Solution Approach 1:
The patent applies second-order distortion matching to convert the harmful second-order harmonic distortion into a beneficial cancellation effect. By carefully designing the LNA to produce equal and opposite second-order distortion components from different signal paths, these harmful distortions cancel each other out, effectively mitigating second-order harmonic interference while maintaining signal quality
Solution Approach 2:
The patent changes key design parameters including transistor sizing ratios, bias current distribution, and impedance matching values to achieve optimal second-order distortion cancellation. By adjusting these parameters, the LNA achieves high second-order intercept points (IP2) while maintaining acceptable power consumption and gain characteristics
2Reliability
If LNA amplifies weak signals, then signal quality is improved, but noise figure increases
Solution Approach 1:
The patent employs dynamic biasing and switching mechanisms that allow the LNA to adapt its operating point based on signal conditions. This dynamic operation enables the LNA to maintain low noise figure for weak signals while providing sufficient gain through controlled amplification stages, preventing noise degradation
Solution Approach 2:
The patent uses asymmetric transistor sizing and biased operating points for the differential pair transistors to optimize the noise figure. By carefully selecting different W/L ratios for NMOS and PMOS transistors and applying asymmetric bias currents, the design achieves minimum noise figure while maintaining the required gain for weak signal amplification
3Object-affected harmful factors
If automated calibration is added, then second-order intercept points are increased, but device complexity increases
Solution Approach 1:
The patent incorporates preliminary calibration during the manufacturing test process to pre-set the optimal transistor sizing ratios and bias conditions for second-order distortion cancellation. This preliminary action embeds the calibration data into the device, allowing the LNA to achieve high second-order intercept points without requiring complex real-time calibration circuitry during operation
Solution Approach 2:
The patent designs the LNA with self-calibrating features where the circuit automatically maintains optimal operating conditions through inherent feedback mechanisms and self-biasing structures. This self-service approach achieves high second-order intercept points without requiring external calibration equipment or complex control logic, thereby limiting the increase in device complexity
Data Source
AI summary
A low noise amplifier (LNA) includes a bank of selectable first transistors and a bank of selectable second transistors complementary to the first transistors. The LNA also includes a plurality of switches to select one or more of the first transistors and to select one or more of the second transistors, the selected first transistors positioned in series with respect to the selected second transistors. The LNA also includes switching logic to control the plurality of switches, to simultaneously vary selection of the first transistors and the second transistors during calibration to substantially match output second-order distortion of the selected first transistors with that of the selected second transistors, to create high second-order intercept points.