Complementary Balanced LNA Topology for Low-Voltage RF Front Ends
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Solution Overview
Problem
Radio frequency front end (RFFE) modules in mobile communication devices face conflicting design requirements of reducing power consumption while maintaining performance parameters dictated by wireless communication standards, particularly in low-noise amplifiers (LNAs), which often compromise on either power or performance.
Innovation Solution
A complementary balanced low-noise amplifier circuit with a single-ended cascoded common-source topology using parallel paths of N-type and P-type transistors, allowing for operation at low supply voltages with high gain and low power consumption, while preserving headroom for output transistors and improving higher-order intercept points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low supply voltages and low currents are used to reduce power consumption, then power consumption is reduced, but performance parameters are compromised
Solution Approach 1:
The amplifier is divided into two separate parallel paths: an N-type path and a P-type path. Each path contains its own common-source transistor and associated circuitry. This segmentation allows each path to operate independently with optimized transistor sizing and biasing, enabling low-power operation while maintaining performance through the combined output of both paths.
Solution Approach 2:
The invention uses a complementary structure combining N-type and P-type transistors in parallel. This composite approach leverages the complementary characteristics of both transistor types to achieve better overall performance than a single-type amplifier could provide at low power consumption levels.
2Device complexity
If a single-ended amplifier topology is used, then device complexity is reduced, but headroom for output transistors is insufficient
Solution Approach 1:
The single-ended amplifier is segmented into two parallel paths (N-type and P-type), each with dedicated output transistors. This segmentation provides sufficient headroom for each transistor in the parallel paths while maintaining the simplicity of a single-ended input and output structure, avoiding the complexity of fully differential topologies.
3Ease of manufacture
If conventional amplifier designs are used, then manufacturing is simpler, but higher-order intercept points (IP2/IP3) performance is degraded
Solution Approach 1:
By segmenting the amplifier into complementary N-type and P-type parallel paths with independently optimized transistors, the design achieves superior IP2 and IP3 performance through the cancellation of even-order distortion products while maintaining manufacturability using standard CMOS processes.
Solution Approach 2:
The complementary parallel architecture combines N-type and P-type transistor paths to exploit their different distortion characteristics, achieving high intercept points through the composite action of both paths while remaining compatible with conventional manufacturing processes.
Data Source
AI summary
A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.