Complementary LO Buffer for Common-Mode Noise Rejection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-performance radio transceivers face challenges in maintaining signal balance and rejecting common-mode noise in local oscillator (LO) buffers, leading to phase errors and unwanted spurs, particularly due to lengthy distribution lines and interference.

Innovation Solution

A local oscillator buffer circuit utilizing a complementary common-source and source-follower stage configuration with matched transconductances, implemented using CMOS technology, to enhance common-mode rejection and phase error correction, thereby reducing power consumption and integrating well with low power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional LO buffer is used, then the LO signal is amplified, but common-mode noise and interference are not rejected, leading to phase errors and spurs

Engineering Contradiction:
Improvesignal balanceVSAvoidcommon-mode noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The LO buffer is divided into two separate complementary stages: a common-source stage for signal amplification and a source-follower stage for common-mode rejection. This segmentation allows each stage to perform its specific function optimally, with the common-source stage providing gain and the source-follower stage rejecting common-mode noise and interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The source-follower stage acts as an intermediary between the common-source amplification stage and the subsequent frequency divider. It mediates by buffering the amplified signal while simultaneously rejecting common-mode noise, thereby protecting the downstream circuitry from phase errors and spurs caused by power supply interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If differential circuitry is used for LO generation, then phase errors are reduced, but coupling of power supply disturbances remains

Engineering Contradiction:
Improvephase accuracyVSAvoidpower supply coupling
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The source-follower stage extracts and rejects common-mode components from the differential signal. By taking out the common-mode noise and interference that couples through the power supply, it allows the differential circuitry to maintain its phase accuracy while being protected from power supply disturbances.

Inventive Principle:
Principle #2Taking out (Extraction)

3Use of energy by moving object

If CMOS technology is used, then power consumption is reduced, but common-mode rejection capability may be limited

Engineering Contradiction:
Improvepower consumptionVSAvoidcommon-mode rejection
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The buffer employs a composite architecture combining two different CMOS transistor configurations (common-source and source-follower) with complementary p-channel and n-channel transistors. This composite structure achieves high common-mode rejection ratio (CMRR) while maintaining low power consumption suitable for modern CMOS fabrication processes.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11658611B2Local oscillator buffer
Publication Date: 2023.05.23 NORDIC SEMICONDUCTOR
  • US11658611B2 patent drawing
  • US11658611B2 patent drawing
  • US11658611B2 patent drawing

AI summary

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.