Complementary Logic Gate for Precise CMOS Signal Symmetrization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for balancing complementary switching signals in CMOS technology are not production-stable, increase energy consumption, and can lead to accuracy reduction and current peaks, especially under high accuracy requirements, due to the inability to generate mutually inverse switching signals without delays and transistor mismatch.
Innovation Solution
A logic gate system comprising AND and OR gates implemented with complementary transistors, where the output is only activated by mutually inverse input signals, allowing for precise signal balancing without time loss, and can be scaled for load requirements using standard CMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If transfer gates or transmission gates are used to delay switching signals for symmetrization, then propagation delay difference is reduced, but energy consumption increases significantly
Solution Approach 1:
The patent changes the logical parameters of the input signals rather than using physical delay elements. By detecting when inputs are logically complementary (one high, one low) and only then activating the output, the circuit achieves symmetrization without energy-intensive delay gates. This parameter-based approach replaces time-based delay mechanisms.
2Loss of time
If ring oscillators or multiple inverters are used to balance switching signals, then propagation times are synchronized, but current spikes are generated that disrupt other circuit parts
Solution Approach 1:
The circuit uses the logical states of the input signals themselves to control the output activation. The output is enabled only when inputs are complementary, allowing the circuit to self-regulate without external current spikes. The logical complementarity detection inherently prevents harmful current transients.
3Loss of time
If transistor driver strength matching is used to symmetrize switching signals, then propagation delay is balanced, but manufacturing tolerances cause instability
Solution Approach 1:
Instead of trying to make transistors identical (direct matching), the patent uses their complementarity (inversion). By designing the circuit to respond to logically complementary input states, it exploits the inherent inverse relationship between paired transistors, making the system robust against manufacturing variations rather than sensitive to them.
4Measurement precision
If design centering and simulation are used to compensate for transistor mismatches, then accuracy is improved, but the solution is not stable in manufacturing and increases complexity
Solution Approach 1:
The patent extracts the essential requirement for symmetrization - logical complementarity detection - from complex compensation mechanisms. By focusing only on detecting when inputs are logically inverse, it removes the need for elaborate simulation-based design centering and manufacturing compensation, achieving accuracy through simplicity.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
The invention relates to a logic gate (30) for the symmetrization of at least two input signals, which comprises a non-inverting input (11), an inverting input (12) and an output (19). The value present on the output (19) corresponds to the inverse of the value present on the inverting input (12). According to the invention, the output (19) is activated only when the value present on the non-inverting input (11) likewise corresponds to the inverse of the value present on the inverting input (12). The invention further relates to a logic gate system which comprises at least two logic gates (30).