Complementary MOS Transistor Structure With PN-Junction Switching
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Solution Overview
Problem
Current transistors, such as FDSOI and Z2FET, face limitations in low-consumption applications and electrostatic discharge protection, lacking performance in certain functions and energy efficiency.
Innovation Solution
A microelectronic device comprising field-effect n-MOS and p-MOS transistors with a PN junction, where the N-doped and P-doped zones form a PN junction, allowing for low energy consumption and high switching speed through controlled voltages applied to the gate and drain/source configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FDSOI transistor structure is used with thin insulating layer, then current leakage is reduced, but device functionality is limited
Solution Approach 1:
The patent merges an n-MOS transistor and a p-MOS transistor into a single integrated device structure, combining two complementary transistor types that share common components (gate, gate oxide, dielectric layer) while maintaining distinct doped zones for each transistor type, thereby achieving enhanced functionality beyond what a single FDSOI transistor can provide
Solution Approach 2:
The integrated device structure serves multiple functions by incorporating both n-MOS and p-MOS transistors in one device, enabling it to perform logic operations, signal processing, and other functions that require complementary transistor pairs, thus improving adaptability while maintaining the low leakage characteristics of FDSOI
2Object-affected harmful factors
If Z2FET transistor is used for ESD protection, then protection function is achieved, but performance is limited
Solution Approach 1:
The patent combines ESD protection functionality with high-performance transistor operation by integrating p-MOS and n-MOS structures that can operate together, allowing the device to provide both protection against electrostatic discharge and improved performance for logic and signal processing applications
3Ease of manufacture
If conventional transistor structure is used, then manufacturing is simple, but switching speed is insufficient
Solution Approach 1:
The patent introduces a vertical dimension by adding a rear gate structure beneath the dielectric layer, creating a dual-gate configuration that enables new control mechanisms for faster switching while maintaining compatibility with existing manufacturing processes through standard layer deposition and doping techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved performance with low current levels, enabling efficient switching and suitable for very low energy consumption electronic systems, surpassing conventional transistors in energy efficiency and functionality.
Implementation Method 1
The device comprises... a second N-doped zone and a second P-doped zone forming a PN junction. It has the particularity that the second N-doped zone and the second P-doped zone form a PN junction.
Implementation Method 2
a field-effect n-MOS transistor comprising a first drain, a first source, a first gate and a first gate oxide... a field-effect p-MOS transistor comprising a second drain, a second source, a second gate and a second gate oxide
Implementation Method 3
a dielectric layer having an upper face in contact with the first N-doped zone, with the second N-doped zone, with the first P-doped zone and with the second P-doped zone
Data Source
AI summary
A microelectronic device includes a field-effect n-MOS transistor, a first N-doped zone, constituting one from among the drain and the source of the n-MOS transistor and a second N-doped zone, constituting the other from among the drain and the source of the n-MOS transistor. The device further includes a field-effect p-MOS transistor, a first P-doped zone, constituting one from among the drain and the source of the p-MOS transistor, a dielectric layer in contact with the doped zones and a rear gate. The n-MOS transistor and the p-MOS transistor are separated by a PN junction.