Complementary Reference Method for Non-Volatile Memory

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Solution Overview

Problem

Non-volatile memory cells with nitride or trap-type storage suffer from threshold voltage narrowing due to charge accumulation and increased hole mobility, leading to instability and reduced reliability, especially under temperature variations and cycling conditions, necessitating additional reference cells for accurate read operations.

Innovation Solution

Implementing a complementary pairing method where two memory cells are grouped into a pair, with one cell programmed and the other erased, allowing them to be compared using a sense amplifier to determine their states, and reserving two reference cells per erase block to maintain high reliability and speed without increasing memory cell size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional single reference cell method is used, then device complexity is reduced, but measurement precision deteriorates due to threshold voltage narrowing

Engineering Contradiction:
Improveread accuracyVSAvoidreference cell configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The reference functionality is segmented into two separate reference cells (first reference cell and second reference cell) with complementary threshold states, allowing independent comparison of memory cell against both references to determine logical state, thereby improving measurement precision through dual-reference validation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different reference cells are assigned different local qualities - one reference cell maintains threshold voltage characteristics for logical 0 comparison while the other maintains characteristics for logical 1 comparison, enabling precise local matching against appropriate reference levels

Inventive Principle:
Principle #3Local quality

2Measurement precision

If complementary pairing method is used, then measurement precision is improved, but device complexity increases due to additional reference cells

Engineering Contradiction:
Improvesignal marginVSAvoidperipheral logic
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The complementary reference cell pair automatically provides self-validation - when one reference cell indicates a logical state, the other reference cell's complementary state confirms or negates this indication, enabling the system to self-determine memory cell state without complex external verification logic

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

Instead of using a single reference cell compared against an intermediate threshold, the invention inverts the approach by using two reference cells with opposite threshold characteristics that directly compare their states against the memory cell, eliminating the need for complex intermediate threshold determination logic

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If threshold voltage window is narrow, then manufacturing precision is improved, but reliability deteriorates due to instability under temperature and cycling variations

Engineering Contradiction:
Improvethreshold stabilityVSAvoidthreshold voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The complementary reference cell configuration provides beforehand cushioning against threshold voltage drift - by maintaining two reference cells with opposite characteristics, the system creates a built-in buffer that compensates for temperature variations and cycling effects, ensuring reliable read operations even when threshold windows narrow due to manufacturing tolerances or aging

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9123419B2Complementary reference method for high reliability trap-type non-volatile memory
Publication Date: 2015.09.01 HALO LSI INC
  • US9123419B2 patent drawing
  • US9123419B2 patent drawing
  • US9123419B2 patent drawing

AI summary

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.