Complementary Resistive Memory Cells for Low-Voltage Read Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory elements in integrated circuits, such as SRAM and CRAM cells, face challenges with reduced read/write margins and increased variability due to smaller transistors, lower power supply voltages, and PVT variations, leading to reliability issues and susceptibility to single event upsets.
Innovation Solution
The integration of non-volatile resistive memory elements, specifically back-to-back or in-line configurations of two-terminal electrochemical metallization memory devices, which utilize redox reactions to form conductive filaments for programming and erasing, providing immunity to single event upsets and low standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistors are scaled towards smaller sizes and lower power supply voltages, then device integration density and power efficiency are improved, but read/write margins for volatile memory elements decrease
Solution Approach 1:
The patent transitions from volatile memory (SRAM) to non-volatile resistive memory, fundamentally changing the memory type parameter. This allows operation at lower power supply voltages while maintaining adequate read/write margins through the resistive switching mechanism, which is less sensitive to voltage scaling than traditional CMOS-based SRAM cells.
Solution Approach 2:
The patent replaces the mechanical/electronic switching mechanism of SRAM (relying on transistor gate control and cross-coupled inverters) with a resistive switching mechanism based on electrochemical metallization. This substitution enables memory operation that is more tolerant of voltage scaling and process variations.
2Area of stationary object
If transistors are scaled towards smaller sizes, then device integration density is improved, but process, voltage, and temperature variations affect memory elements more severely
Solution Approach 1:
The patent changes the memory technology parameter from volatile CMOS-based SRAM to non-volatile resistive memory, which exhibits different sensitivity characteristics to PVT variations. The resistive switching mechanism provides more robust operation under process, voltage, and temperature variations, improving memory yield despite continued transistor scaling.
3Speed
If volatile memory elements are used, then fast read/write operation is achieved, but immunity to single event upsets is lost
Solution Approach 1:
The patent replaces the volatile SRAM cell structure with a non-volatile resistive memory structure that uses electrochemical metallization. This substitution provides single event upset immunity while maintaining fast operation through the rapid formation and dissolution of conductive filaments in the resistive switching layer.
Solution Approach 2:
The resistive memory structure inherently provides non-volatility and radiation hardness through its physical mechanism of conductive filament formation. The memory state is maintained without power and is resistant to single event upsets, eliminating the need for complex error correction or redundancy schemes required by volatile memory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of integrated circuits by providing non-volatile memory that retains its state regardless of power supply, offering immunity to single event upsets and maintaining low standby current, thus improving memory yield and system performance.
Implementation Method 1
two-terminal electrochemical metallization memory devices, which utilize redox reactions to form conductive filaments for programming and erasing
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.