Complementary RRAM Cell Architecture for Sneak Current Suppression
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices face challenges in scaling due to sneak parasitic currents and destructive read operations in existing architectures, which limit their performance and lifespan.
Innovation Solution
A complimentary RRAM architecture without a select device is used, featuring two resistive elements of opposite polarity connected in series, with a pass transistor that scales linearly with the resistive elements, allowing for simultaneous SET/RESET operations and reducing the need for additional circuitry, thereby suppressing sneak currents and maintaining data integrity during reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If complementary resistive switches are used to suppress sneak parasitic currents, then sneak path currents are suppressed without select devices, but destructive read occurs requiring additional SET/RESET operations
Solution Approach 1:
A read-disturb compensation circuit is introduced as an intermediary component that detects and compensates for resistance changes caused by read operations. This circuit monitors the resistance state of memory cells and performs corrective SET/RESET operations to restore the original state, thereby compensating for the destructive effect of read operations without requiring additional write cycles
2Object-affected harmful factors
If 1T1R architecture with select transistor is used, then sneak parasitic currents are suppressed, but scaling is limited due to current requirements for forming/SET/RESET operations
Solution Approach 1:
The select transistor is extracted/removed from the memory cell structure. Instead of using a select transistor to control current flow, the patent employs a different cell configuration where the complementary resistive switches themselves manage current paths, eliminating the need for additional select devices and enabling better scaling
3Area of stationary object
If RRAM cell size is reduced, then bit-cell area decreases, but more current is required through pass transistor for forming/SET/RESET operations
Solution Approach 1:
The patent transitions from planar scaling to vertical stacking by implementing a 3D stacked memory architecture. Multiple memory cell layers are stacked vertically, allowing bit-cell area reduction while maintaining current requirements through the vertical current paths in the stacked structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient scaling of RRAM devices, reduces the number of write operations required, and maintains data integrity during reads, improving performance and extending the lifespan of memory cells by eliminating the need for destructive read operations.
Implementation Method 1
a variable resistance material having different resistance states depending on an applied voltage
Implementation Method 2
the first resistive element has a first resistance state and the second resistive element has a second resistance state, wherein the first resistance state has a higher resistance than the second resistance state
Data Source
AI summary
A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line, wherein the first and second resistive elements are coupled between different metal layers; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.