Complementary Signal Slope Adjustment for Duty Cycle Correction
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Solution Overview
Problem
In memory applications, duty cycle distortions in clock signals due to PVT variations and silicon interface effects lead to errors in data retrieval, as the duty cycle of clock signals often deviates from the ideal 50% required for proper data alignment and processing.
Innovation Solution
A circuit with a slope adjustment mechanism that measures duty cycle and cross-point distortions, adjusting drive strengths of circuit stages to generate complementary signals with corrected duty cycles and reduced distortions, ensuring accurate data alignment and transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the controller generates clock signals with ideal 50% duty cycle, then data alignment accuracy is improved, but process-voltage-temperature variations and silicon interface effects cause duty cycle distortion that worsens data retrieval reliability
Solution Approach 1:
The patent implements a feedback mechanism where the memory die measures the duty cycle of received clock signals and compares it against a target duty cycle. Based on this comparison, the memory die adjusts its data alignment timing to compensate for duty cycle deviations, ensuring reliable data retrieval even when the controller generates imperfect clock signals.
Solution Approach 2:
The patent dynamically changes the timing parameters for data alignment based on the measured duty cycle of the clock signals. By adjusting the alignment timing in response to duty cycle variations, the system maintains accurate data sampling despite PVT variations and interface effects that cause duty cycle distortion.
2Productivity
If the duty cycle of clock signals shifts away from 50% during data retrieval, then data valid window shrinks causing sampling errors, but adding duty cycle correction circuits increases device complexity
Solution Approach 1:
The memory die performs self-correction by measuring its own data alignment accuracy and adjusting its timing accordingly. This self-service approach allows the system to maintain high data transfer reliability without requiring complex external correction circuits, as the memory die autonomously compensates for duty cycle variations.
Solution Approach 2:
The patent introduces an intermediary measurement and adjustment mechanism that sits between the clock signal reception and data alignment processes. This intermediary layer measures the actual duty cycle and uses it to mediate the timing of data alignment, preventing sampling errors without requiring major architectural changes.
3Reliability
If RC components filter out clock signal edges due to duty cycle deviation, then signal integrity deteriorates, but increasing signal strength to compensate increases power consumption
Solution Approach 1:
The patent performs preliminary measurement of the clock signal duty cycle before data alignment occurs. By knowing the duty cycle characteristics in advance, the system can pre-adjust the data alignment timing to account for potential RC filtering effects, maintaining signal integrity without needing to increase signal strength and consume additional power.
Data Source
AI summary
A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.