Complementary Switched Capacitor Circuit for Linear Capacitance

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Solution Overview

Problem

Prior art switched capacitors exhibit nonlinearity in their equivalent capacitance due to parasitic capacitors, which is undesirable in many applications.

Innovation Solution

A switched capacitor circuit design incorporating N-type and P-type switches, transmission gates, and specific resistor configurations to maintain linearity in both states, utilizing complementary transistors and capacitors to offset nonlinearities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a prior art switched capacitor uses a single NMOS transistor switch, then the circuit is simple, but the equivalent capacitance becomes nonlinear due to parasitic capacitors

Engineering Contradiction:
Improvecircuit structureVSAvoidcapacitance linearity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The single NMOS switch is segmented into two complementary switches: an NMOS transistor and a PMOS transistor. Each transistor has its own parasitic capacitors, but they are complementary in nature. When both switches operate together, their parasitic effects cancel out, achieving linear capacitance without increasing overall circuit complexity significantly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention uses the complementary parasitic capacitors of the PMOS transistor to counterbalance the parasitic capacitors of the NMOS transistor. The nonlinearities introduced by each transistor's parasitic capacitance are equal in magnitude but opposite in sign, causing them to offset each other and produce a linear equivalent capacitance.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

2Manufacturing precision

If the switched capacitor uses complementary NMOS and PMOS switches, then capacitance linearity is improved, but device complexity increases

Engineering Contradiction:
Improvecapacitance linearityVSAvoidcircuit structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The NMOS and PMOS switches are merged into a single complementary switch pair that operates together as one functional unit. Both switches are controlled by complementary control signals and work simultaneously to provide the switching function, reducing the overall complexity compared to using separate switches or more complex circuit topologies.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The complementary switch pair serves multiple functions: it provides the primary switching function, compensates for parasitic nonlinearities, and maintains low on-resistance in both states. This multi-functionality reduces the need for additional compensation circuits or components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If parasitic capacitors are present in the switch, then the circuit is easier to manufacture, but the equivalent capacitance becomes nonlinear

Engineering Contradiction:
Improveswitch implementationVSAvoidcapacitance linearity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The invention converts the harmful effect of parasitic capacitors into a beneficial one. Instead of trying to eliminate or minimize parasitic capacitors, the design deliberately uses complementary switches whose parasitic capacitors are inherently present but opposite in sign. The parasitic effects that would normally degrade performance are transformed into a mechanism for achieving linearity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS10734973B2Switched capacitor circuit and method thereof
Publication Date: 2020.08.04 REALTEK SEMICON CORP
  • US10734973B2 patent drawing
  • US10734973B2 patent drawing
  • US10734973B2 patent drawing

AI summary

A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.