Complementary Transistor Circuit for Low Differential Delay
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Solution Overview
Problem
In transistor circuits, a differential delay between non-inverted and inverted outputs is caused by the need to generate an inverted input from a non-inverted input, which hinders the increase in data transfer speed.
Innovation Solution
A transistor circuit is designed with a first transistor that outputs a non-inverted signal and a second transistor that outputs an inverted signal based on the same input signal, eliminating the need for an inversion unit and thereby reducing differential delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an inversion unit is used to generate an inverted input from a non-inverted input, then a differential output can be generated, but a differential delay is caused between the non-inverted output and the inverted output
Solution Approach 1:
The invention extracts and eliminates the inversion unit from the signal path. By removing the component that causes the differential delay (the inversion unit that processes the non-inverted input to create an inverted input), the patent directly reduces the differential delay between output signals while maintaining the ability to generate differential outputs through a different architecture.
Solution Approach 2:
Instead of inverting the input signal before processing (the conventional approach), the patent inverts the approach by processing the same non-inverted input signal through two different transistor configurations simultaneously - one that produces a non-inverted output and another that produces an inverted output. This reverse approach eliminates the delay caused by sequential inversion processing.
2Ease of operation
If an inversion unit is used to generate an inverted input, then a differential output can be generated, but the circuit size increases
Solution Approach 1:
The invention extracts and removes the dedicated inversion unit from the circuit architecture. By eliminating this separate component and integrating the inversion function directly into the transistor processing stage, the patent reduces the overall circuit size while maintaining differential output capability.
Solution Approach 2:
The patent merges the inversion function with the main signal processing transistors. Instead of having a separate inversion unit, the invention combines the signal processing and inversion operations into a single integrated transistor stage, thereby reducing the total circuit area required.
3Ease of operation
If an inversion unit is used to generate an inverted input, then a differential output can be generated, but power consumption increases
Solution Approach 1:
The invention extracts and eliminates the inversion unit that consumes power. By removing this dedicated component and integrating its function into the main transistor processing stage, the patent reduces the total power consumption of the circuit while maintaining differential output generation capability.
Solution Approach 2:
The patent merges the inversion operation with the main signal processing function in a single transistor stage. This consolidation eliminates the need for separate power-consuming inversion circuits, thereby reducing overall power consumption while achieving the same differential output result.
Data Source
AI summary
A differential delay between a non-inverted output and an inverted output of a transistor circuit is reduced.A transistor circuit includes a first transistor and a second transistor. The first transistor receives an input signal as an input, and outputs a first output signal. The second transistor receives the input signal as an input, and outputs a second output signal, which is in a reverse polarity with respect to the first output signal, on the basis of a bias that causes the second transistor to operate in a complementary manner with respect to the first transistor. The first transistor may include a first terminal, a second terminal, and a first control terminal that controls a current that flows between the first terminal and the second terminal. The second transistor may include a third terminal, a fourth terminal, and a second control terminal that controls a current that flows between the third terminal and the fourth terminal. The first output signal may be output from the first terminal, the second output signal may be output from the third terminal, and the input signal may be input to the second terminal of the first transistor and the second control terminal of the second transistor.