Completion Packet Return Based on Cache Eviction or Flush
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Solution Overview
Problem
Existing processor coherent protocols are not designed to support low overhead commitment of coherently accessed non-volatile memory, leading to increased latency when writing data to persistent storage, as they wait for data to be actually written to ensure correctness, whereas volatile memory protocols can indicate write completion immediately after data receipt.
Innovation Solution
A system protocol that allows a non-volatile memory controller to differentiate between cache capacity eviction and flush operations by returning a completion packet before or after data is written to memory based on a field in the data packet, enabling immediate completion indication for cache evictions and ensuring commitment for flush operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller waits for data to be actually written to persistent memory before indicating write completion, then data correctness is ensured, but write latency increases
Solution Approach 1:
The patent dynamically adjusts the write completion indication timing based on the operation type. For cache evictions, completion is indicated immediately without waiting for persistent memory write, while for flush operations, completion is indicated only after successful write to persistent memory. This dynamic behavior resolves the contradiction by adapting the reliability guarantee to the specific operation's requirements.
Solution Approach 2:
The patent applies different completion semantics to different types of write operations. Cache eviction operations receive immediate completion indication (local optimization for speed), while flush operations receive completion only after persistent write (local optimization for reliability). This local differentiation resolves the contradiction by applying the appropriate level of guarantee to each operation type.
2Productivity
If the controller returns completion packet immediately after data receipt for cache evictions, then write speed improves, but data commitment to persistent memory is delayed
Solution Approach 1:
The patent dynamically determines when to return the completion packet based on the operation type indicated in the data packet. For cache evictions, the completion packet is returned immediately after data receipt, improving write speed. For flush operations, the completion packet is returned only after successful persistent memory write, ensuring data commitment. This dynamic approach resolves the contradiction between speed and reliability.
Solution Approach 2:
The patent segments the write operation handling into different paths based on operation type. Cache eviction operations follow a fast path with immediate completion indication, while flush operations follow a reliable path with completion after persistent write. This segmentation allows the system to optimize for speed where appropriate while maintaining reliability where required.
Data Source
AI summary
A completion packet may be returned before a data packet is written to a memory, if a field of the data packet indicates the data packet was sent due to a cache capacity eviction. The completion packet is returned after the data packet is written to the memory, if the field indicates the data packet was sent due to a flush operation.