Storage Controller Completion Queue Placement for Low I/O Latency
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Solution Overview
Problem
Existing storage systems face challenges in optimizing input/output latency and bandwidth due to inefficiencies in managing completion entries between host caches and memory, leading to performance degradation.
Innovation Solution
A storage device with a non-volatile memory and a storage controller that selectively posts completion entries to either host memory or cache based on latency, using interrupt vectors to optimize processing by determining the location for caching and transmitting interrupts to prioritize cached entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If completion entries are posted to host memory, then storage capacity is sufficient, but input/output latency increases
Solution Approach 1:
The patent segments the completion queue storage into multiple locations: cache memory for high-priority/low-latency entries and main memory for low-priority/high-capacity entries. The storage controller selectively posts completion entries to different locations based on priority levels, command types, and cache status, thereby resolving the contradiction between storage capacity and access latency.
Solution Approach 2:
The patent applies local quality by assigning different storage characteristics to different completion entry types. High-priority entries receive premium storage in cache memory with fast access, while low-priority entries are stored in main memory. This differentiated approach optimizes the overall system performance by matching storage quality to entry priority.
2Loss of time
If completion entries are cached in host cache, then input/output latency is reduced, but cache memory capacity is limited
Solution Approach 1:
The patent implements dynamic completion queue management where the storage controller continuously monitors cache memory status, entry priority levels, and system workload. This dynamic approach allows the system to adaptively allocate cache space to high-priority entries while maintaining the ability to overflow to main memory when cache capacity is exhausted, thus optimizing latency without being constrained by fixed cache capacity.
Solution Approach 2:
The storage controller performs preliminary assessment of completion entries before posting them to cache memory, evaluating factors such as priority level, command type, and current cache status. This preliminary action prevents cache overflow issues and ensures that only suitable entries are placed in cache, maximizing the utilization of limited cache capacity while maintaining low latency for critical entries.
3Productivity
If selective posting to cache or memory is implemented, then input/output performance is optimized, but device complexity increases
Solution Approach 1:
The patent implements self-service mechanisms where the storage controller automatically manages completion queue posting decisions without requiring complex external intervention. The controller uses predefined priority rules, command type classifications, and cache status monitoring to make autonomous posting decisions, thereby optimizing performance while keeping the control logic manageable and relatively simple.
4Productivity
If interrupt vectors are used to prioritize cached entries, then processing efficiency is improved, but system complexity increases
Solution Approach 1:
The patent applies partial action by using interrupt vectors selectively only for cached completion entries that require high-priority processing. Not all completion entries trigger interrupts; only those in cache memory with high priority do. This partial application of interrupt mechanisms provides processing efficiency for critical entries while avoiding the overhead of managing interrupts for all entries, thus balancing efficiency gains with manageable complexity.
Data Source
AI summary
Provided are a storage device, an operation method of the storage device, and an electronic system including the storage device. The storage device includes a non-volatile memory device, and a storage controller configured to control the non-volatile memory device, execute a command from a host, select a location to which a completion entry for the command is to be written from among a memory and at least one cache of the host, and transmit, to the host, an interrupt including an interrupt vector number indicating the location to which the completion entry is to be written.