Complex Logic Cell Sharing Gate Electrodes to Reduce Routing Congestion

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Solution Overview

Problem

Current semiconductor design tools face challenges in efficiently placing and routing standard cells due to routing congestion and timing constraints, particularly in dense arrangements of complex logic gate circuits, which affects layout space allocation and performance.

Innovation Solution

The integration of complex logic cells, which share common input signals and power nodes with standard cells, reduces the number of required standard cells and alleviates routing congestion by incorporating first and second logic circuits with shared gate electrodes, thereby improving layout space efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If multiple standard cells are used to implement complex logic circuits, then the logic functionality is achieved, but routing congestion increases and layout space efficiency decreases

Engineering Contradiction:
Improverouting freedomVSAvoidlayout space
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent combines multiple standard cells into a single complex logic cell that shares common input signals and power nodes. Specifically, the complex logic cell integrates first and second logic circuits that share a common gate electrode structure and common power supply connections, thereby reducing the total number of cells required and improving layout space efficiency while maintaining the necessary logic functionality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The complex logic cell is designed to perform multiple logic functions within a single cell structure. By incorporating shared gate electrodes and common power nodes, the cell can implement various logic operations (such as AOI - AND-OR-Inverter) that would traditionally require multiple separate standard cells, thus achieving multi-functionality and reducing routing congestion

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple standard cells are used to implement complex logic circuits, then the logic functionality is achieved, but the number of required cells increases reducing manufacturing efficiency

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidnumber of standard cells
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple standard cells into a single complex logic cell structure. The complex logic cell contains first and second logic circuits that share common gate electrodes and power nodes, reducing the total cell count from multiple standard cells to one integrated cell, thereby improving manufacturing efficiency and reducing placement complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The complex logic cell is segmented into distinct logic circuits (first logic circuit and second logic circuit) within a unified structure. This segmentation allows each logic circuit to be independently designed and optimized while sharing common resources like gate electrodes and power nodes, achieving both functional complexity and manufacturing efficiency

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10586809B2Integrated circuit including complex logic cell
Publication Date: 2020.03.10 SAMSUNG ELECTRONICS CO LTD
  • US10586809B2 patent drawing
  • US10586809B2 patent drawing
  • US10586809B2 patent drawing

AI summary

An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.