Complex Oxide Nanodots for Memory Charge Retention

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Solution Overview

Problem

Conventional nonvolatile memory technologies face challenges in charge retention due to defects in tunneling dielectric layers, leading to scaling limitations and reliability issues in memory devices.

Innovation Solution

The use of complex oxide nanodots, specifically strontium titanate (STO) nanodots with a perovskite structure, formed through alternating pulse deposition methods, provides discrete charge trapping sites that minimize charge leakage and enhance charge retention capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the tunneling dielectric layer thickness is reduced to enable vertical scaling, then programming speed increases and lower voltage operation is achieved, but charge retention capability seriously degrades

Engineering Contradiction:
Improveprogramming speedVSAvoidcharge retention capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The charge trapping layer is segmented into discrete nanodots rather than a continuous layer. This segmentation isolates charge storage into individual confined regions, preventing charge leakage paths that would exist in thin continuous dielectric layers, thereby maintaining charge retention while enabling thin tunneling oxide for fast programming

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The nanodots provide localized charge trapping sites with specific material properties (complex oxide composition) that create deep potential wells for charge confinement. This local quality enhancement at the nanodot sites compensates for the reduced overall dielectric thickness, maintaining charge retention capability while enabling scaling

Inventive Principle:
Principle #3Local quality

2Length of stationary object

If conventional SONOS dielectric layers are used with thin tunneling oxide, then vertical scaling is achieved, but charge retention properties intrinsically deteriorate

Engineering Contradiction:
Improvetunneling oxide thicknessVSAvoidcharge retention properties
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The charge trapping layer uses composite materials (complex oxides such as SrTiO3, BaTiO3, Pb(Zr,Ti)O3) with specific perovskite crystal structures that provide superior charge confinement properties. These materials have higher dielectric constants and create deeper potential wells compared to conventional SiN, enabling reliable charge retention even with thin tunneling oxide layers

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The invention changes the material parameters of the charge trapping layer from conventional SiN to complex oxides with higher dielectric constants and appropriate band offsets. This parameter change creates deeper charge traps and improves charge confinement, compensating for the reduced tunneling oxide thickness and maintaining charge retention capability

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of STO nanodots in charge trapping layers offers superior charge storage and retention properties, reducing the sensitivity to defects and improving the reliability of memory devices by providing localized, deep charge traps with high dielectric constants and appropriate energy band characteristics.

Implementation Method 1

a second dielectric layer comprising a material having a perovskite structure over the first dielectric layer

Methodology Applied
Scientific EffectElectrostatic confinement: Electrostatics

Implementation Method 2

complex oxide nanodots, specifically strontium titanate (STO) nanodots with a perovskite structure

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS8203179B2Device having complex oxide nanodots
Publication Date: 2012.06.19 MICRON TECHNOLOGY INC
  • US8203179B2 patent drawing
  • US8203179B2 patent drawing
  • US8203179B2 patent drawing

AI summary

Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric.