Complex-Pole Load for Concurrent Image Rejection and Channel Selection

The patent replaces bulky physical inductors and transformers with an active circuit implementation using transistors (M1-M4) configured as a complex-pole load. This active implementation synthesizes the desired impedance characteristics through transistor operation rather than relying on passive magnetic components, thereby achieving the same voltage headroom and parasitic compensation effects without the associated die area penalty.

The patent changes the implementation approach from passive L-element (inductor) to active transistor-based impedance synthesis. By adjusting transistor bias conditions and configuration, the circuit dynamically generates the required complex pole behavior, allowing voltage headroom optimization without fixed physical component constraints that occupy die area.

The patent merges the functions of input matching, pre-gain, and noise figure optimization into a single integrated complex-pole load circuit implemented with transistors M1-M4. This consolidation eliminates the need for separate external high-Q inductors and passive pre-gain stages, reducing sensitivity to external component variations while maintaining the desired noise figure and gain characteristics through active circuit design.

The complex-pole load circuit performs multiple functions simultaneously: it provides narrowband input matching, passive pre-gain, and noise figure optimization all within a single transistor-based structure. This multi-functionality replaces what would traditionally require multiple external passive components, thereby reducing device complexity and external component sensitivity.

The patent segments the receiver functions into distinct blocks: the LNA (M1-M2) handles low-noise amplification with optimized noise figure, while the complex-pole load (M1-M4) handles I/Q generation and channel selection. This segmentation allows each block to be optimized independently, preventing the 3 dB gain loss that would occur if I/Q generation were embedded in the LNA, while still maintaining compact area through current reuse.

The complex-pole load circuit acts as an intermediary between the LNA and the mixing stage. It receives the LNA output and provides both the I/Q generation and the channel selection function, thereby mediating the signal path in a way that preserves LNA gain and noise figure performance while still achieving compact integration.

The patent merges baseband channel selection and image rejection functions into the RF current-reuse path by implementing them in the complex-pole load circuit (M1-M4) that operates in the RF domain. This integration allows these functions to be performed using the existing RF signal currents without requiring separate high-power baseband processing stages, thereby maintaining RF performance while significantly reducing baseband power consumption.

The complex-pole load performs channel selection and image rejection as preliminary actions in the RF domain before the signal reaches the baseband stage. By filtering and selecting channels early in the RF path using the transistor-based complex pole, the circuit prevents the need for high-power baseband filtering and processing, thus reducing overall baseband power consumption while maintaining signal integrity.