Complex Vector FMA Circuit Using SIMD Multiplexed Data Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processor architectures face inefficiencies in executing complex vector multiplication and fused multiply-add operations due to the high memory and register resource requirements for double-sized products, and the need for combination of shuffle instructions and multiply-add operations for complex number multiplication.
Innovation Solution
Implementing complex vector multiply (CVMUL) and complex vector fused multiply-add (CVFMA) operations in a single instruction multiple data (SIMD) processor by adding minimal hardware, specifically two multiplexers to the existing execution circuitry, using a grid of fused multiply-add (FMA) circuits to perform these operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If regular multiplication instructions are used for complex number multiplication, then the operation can be performed, but it requires combination of shuffle instructions and fused multiply add, increasing instruction complexity and execution time
Solution Approach 1:
The patent combines shuffle operations and multiplication operations into a unified complex vector multiply instruction. The execution circuitry integrates data shuffling and multiplication in a single operational sequence, eliminating the need for separate shuffle instructions before multiplication. This merging reduces the total number of instructions and improves execution efficiency.
Solution Approach 2:
The execution circuitry is designed to handle both real and imaginary component multiplications using the same FMA units. The circuitry universally processes complex number operations by automatically routing real parts to real multiplication units and imaginary parts to imaginary multiplication units, eliminating the need for separate instruction sequences for different operation types.
2Measurement precision
If double-sized products are generated for precise multiplication results, then calculation precision is improved, but memory and register resources required increase significantly
Solution Approach 1:
The patent segments the complex multiplication results into separate real and imaginary components, each stored in dedicated register lanes. Instead of storing full double-precision products that consume excessive memory, the results are partitioned into component parts that can be stored more efficiently in vector registers, reducing overall memory and register resource requirements.
Solution Approach 2:
The patent transforms the storage requirement from a single double-precision value to two single-precision values (real and imaginary components). This dimensional transformation allows the results to be stored in the same register width as the input operands, rather than requiring double the width, thereby reducing memory and register resource consumption while maintaining precision.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Disclosed embodiments relate to efficient complex vector multiplication. In one example, a processor comprises fetch and decode circuitry to fetch and decode an instruction having fields to specify an accumulation complex vector, a multiplier complex vector, and a multiplicand complex vector, and execution circuitry, responsive to the decoded instruction, to generate a double-even multiplicand vector by duplicating even elements of the specified multiplicand complex vector into adjacent more significant odd element positions, multiply elements of the multiplier complex vector and elements from corresponding positions of the double-even multiplicand vector to generate corresponding products, accumulate the products with elements from corresponding positions of the destination complex vector, and store a result in a destination storage location.