3D IC Interconnects with Compliant Dielectric Stress Absorption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D IC packaging techniques face challenges such as high costs, complex manufacturing processes, and interconnect failures due to thermal and vibrational stresses, limiting the adoption of cost-effective solutions for stacking and vertically interconnecting multiple chips, particularly for image sensors and processors.
Innovation Solution
A wafer-level 3D IC integration package that uses a handler with conductive elements extending through a substrate and a compliant dielectric material to securely and electrically couple multiple IC devices, such as image sensors and processors, reducing thermal and mechanical stresses and enabling direct memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D IC packaging techniques (Via-First, Via-Last, Via-middle) are used, then through-silicon via's can be formed, but the manufacturing process becomes complex and costly
Solution Approach 1:
The patent extracts the complex lithographic processes from the TSV formation and replaces them with simple mechanical drilling and molding operations. The interconnect structure is separated into discrete molded components that can be assembled without complex semiconductor fabrication processes, thereby reducing manufacturing complexity while maintaining reliability
Solution Approach 2:
The patent employs cost-effective molded interconnect structures that can be manufactured using inexpensive molding processes rather than expensive CMOS lithography. These molded interconnects serve as disposable or replaceable components that enable 3D integration without requiring billions of dollars in R&D infrastructure
2Reliability
If rigid interconnect structures are used in 3D packaging, then electrical connection is achieved, but thermal and vibrational stresses cause interconnect failure
Solution Approach 1:
The patent changes the physical parameters of the interconnect structure by introducing compliance through molded materials and flexible interconnect designs. This allows the interconnects to accommodate thermal expansion and vibrational stresses through elastic deformation rather than rigid failure, thereby maintaining reliability under stress conditions
Solution Approach 2:
The patent incorporates stress-absorbing features in the molded interconnect structures before assembly, such as compliant material layers and flexible geometries that preemptively cushion against thermal and vibrational stresses. This beforehand cushioning prevents stress concentration and interconnect failure during operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a cost-effective and reliable method for 3D integration of IC devices, enhancing electrical performance, reducing manufacturing costs, and improving yield by using compliant dielectric materials and through-polymer-interconnects that absorb stresses and provide efficient signal coupling.
Implementation Method 1
compliant dielectric materials and through-polymer-interconnects that absorb stresses
Data Source
AI summary
A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.