Compliant Dielectric Layer for IC Package Thermal Stress
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Solution Overview
Problem
Integrated circuit (IC) packages face mechanical stress and damage due to thermal expansion mismatch between semiconductor materials and substrates, limiting die and interposer sizes and causing cracking and delamination.
Innovation Solution
Incorporation of a compliant dielectric layer with a coefficient of thermal expansion matching the substrate, allowing for lateral movement and reducing thermal/mechanical stresses, which is achieved by using organic dielectric materials like elastomers or Polyimide, and forming electrically conductive vias through the layer for signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the die or interposer size is increased, then the signal routing capability and interconnect density are improved, but the mechanical stress and thermal expansion mismatch problems worsen, causing cracking and delamination
Solution Approach 1:
The patent changes the physical parameters of the dielectric layer by selecting materials with specific coefficients of thermal expansion (CTE) that match the substrate. This parameter matching allows the dielectric layer to expand and contract at the same rate as the substrate during thermal cycling, eliminating mechanical stress and preventing cracking and delamination in larger packages
Solution Approach 2:
The patent employs composite material structures where an organic dielectric material is used in conjunction with the substrate and semiconductor materials. This composite approach allows selection of materials with complementary properties, particularly matching CTE values between layers, thereby resolving the thermal expansion mismatch problem while enabling larger package sizes
2Strength
If rigid dielectric materials are used, then the structural support and electrical insulation are improved, but the thermal expansion mismatch causes mechanical stress and cracking
Solution Approach 1:
The patent transitions from rigid dielectric materials to organic dielectric materials with specific CTE parameters that match the substrate. This parameter change maintains structural support and electrical insulation properties while eliminating thermal expansion stress by ensuring all layers expand and contract at the same rate during temperature cycles
3Reliability
If the die or interposer size is limited to reduce mechanical stress, then the reliability is improved, but the signal routing capability and interconnect density are reduced
Solution Approach 1:
The patent changes the CTE parameter of the dielectric layer to match the substrate, which eliminates thermal expansion stress. This allows the die or interposer size to be increased beyond previous limitations while maintaining reliability, thereby improving signal routing capability and interconnect density without causing cracking or delamination
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compliant dielectric layer reduces mechanical stress, increases yield, and enables larger IC package sizes by allowing thermal expansion compatibility with substrates, thereby enhancing reliability and scalability.
Implementation Method 1
During the manufacturing process, such packages undergo temperature cycles (e.g., heating and cooling), which causes thermal expansion of the semiconductor material of the die in a wafer level package, and of the die and interposer in an interposer-enabled wafer level package.
Implementation Method 2
The compliant dielectric layer has a deformability that is greater than a deformability of the semiconductor material body
Data Source
AI summary
Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.